/*****************************************************************************
 *                                                                           *
 *        **********                                                         *
 *       ************                                                        *
 *      ***        ***                                                       *
 *      ***   +++   ***                                                      *
 *      ***   + +   ***                                                      *
 *      ***   +                            CHIPCON CC1010                    *
 *      ***   + +   ***           HARDWARE REGISTER DEFINITION FILE          *
 *      ***   +++   ***                                                      *
 *      ***       ***                                                        *
 *       ***********                                                         *
 *        *********                                                          *
 *                                                                           *
 *****************************************************************************
 * The Chipcon Hardware Register definition file is a header file defining   *
 * mnemonic names for CC1010 SFR registers, individually addressable SFR     *
 * bits and interrupt service routine addresses.                             *
 *****************************************************************************
 * Author:              ROH                                                  *
 *****************************************************************************
 * Revision history:                                                         *
 * 1.0  2002/04/01      First Public Release                                 *
 *                                                                           *
 * $Log: Reg1010.h,v $
 * Revision 1.1  2002/10/14 11:49:08  tos
 * Initial version in CVS.
 *
 *                                                                           *
 ****************************************************************************/
#ifndef WIN32
#ifndef REG1010_H

#define REG1010_H       // Only include this header file once

/* Real clock Timer Control */
sfr RTCON     = 0xED;

/*A/D*/
sfr ADCON     = 0x93;
sfr ADDATL    = 0x94;
sfr ADDATH    = 0x95;
sfr ADCON2    = 0x96;
sfr ADTRH     = 0x97;


/* Chip version */
sfr CHVER     = 0x9F;

/* Triac */
sfr TRICON    = 0x9A;
sfr TRI3      = 0x9B;
sfr TRI2      = 0x9C; 
sfr TRI1      = 0x9D;
sfr TRI0      = 0x9E;

/* Flash write */
sfr FLADR     = 0xAE;
sfr FLCON     = 0xAF;
sfr FLTIM     = 0xDD;

/* SPI */
sfr SPCR      = 0xA1;
sfr SPDR      = 0xA2;
sfr SPSR      = 0xA3;

/* Timer 2 / 3 */
sfr TCON2     = 0xA9;
sfr T2PRE     = 0xAA;
sfr T3PRE     = 0xAB;
sfr T2        = 0xAC;
sfr T3        = 0xAD;

  /*  Encryption / decryption initialisation vector */
sfr CRPINI0   = 0xB4;
sfr CRPINI1   = 0xB5;
sfr CRPINI2   = 0xB6;
sfr CRPINI3   = 0xB7;
sfr CRPINI4   = 0xBC;
sfr CRPINI5   = 0xBD;
sfr CRPINI6   = 0xBE;
sfr CRPINI7   = 0xBF;

/*    -- RF Control */
sfr RFCON     = 0xC2;

/* -- Encryption / decryption initialisation vector */
sfr CRPCON    = 0xC3;
sfr CRPKEY    = 0xC4;
sfr CRPDAT    = 0xC5;
sfr CRPCNT    = 0xC6;

/* -- Main config register */
sfr RFMAIN    = 0xC8;

/* -- RF Data input / output */
sfr RFBUF     = 0xC9;

/* -- Frequency multiply registers */
sfr FREQ_0A   = 0xCA;
sfr FREQ_1A   = 0xCB;
sfr FREQ_2A   = 0xCC;
sfr FREQ_0B   = 0xCD;
sfr FREQ_1B   = 0xCE;
sfr FREQ_2B   = 0xCF;

/* -- Power control */
sfr X32CON    = 0xD1;

/* -- Watchdog */
sfr WDT       = 0xD2;

/* -- Preamble */
sfr PDET      = 0xD3;
sfr BSYNC     = 0xd4;

/* -- Modulator / Demodulator conntrol */
sfr MODEM2    = 0xD9;
sfr MODEM1    = 0xDA;
sfr MODEM0    = 0xDB;

/* -- Matching of cap array */
sfr MATCH     = 0xDC;

/* -- Control signals */
sfr CURRENT   = 0xE1;
sfr PA_POW    = 0xE2;
sfr PLL       = 0xE3;
sfr LOCK      = 0xE4;
sfr CAL       = 0xE5;
sfr FREND     = 0xEE;

/* -- Frequency shaping delay */
sfr FSDELAY   = 0xE9;

/* -- Frequency separation registers */
sfr FSEP0     = 0xEA;
sfr FSEP1     = 0xEB;

/* -- Frequency synthesiser control */
sfr FSCTRL    = 0xEC;

/* -- Frequency shaping */
sfr FSHAPE7   = 0xF1;
sfr FSHAPE6   = 0xF2;
sfr FSHAPE5   = 0xF3;
sfr FSHAPE4   = 0xF4;
sfr FSHAPE3   = 0xF5;
sfr FSHAPE2   = 0xF6;
sfr FSHAPE1   = 0xF7;

/* -- Test and status registers */
sfr TEST0     = 0xF9;
sfr TEST1     = 0xFA;
sfr TEST2     = 0xFB;
sfr TEST3     = 0xFC;
sfr TEST4     = 0xFD;
sfr TEST5     = 0xFE;
sfr TEST6     = 0xFF;
sfr TESTMUX   = 0xEF;

/* The rest! */
sfr ACC    = 0xE0;

/*Ports*/
sfr P0     = 0x80; /*Only P0.3 to P0.3 exists*/
sfr P1     = 0x90; /*P1.0 to P1.7*/
sfr P2     = 0xA0;
sfr P3     = 0xB0; /*Only P3.0 to P3.5 exists*/

sfr P0DIR  = 0xA4;
sfr P1DIR  = 0xA5;
sfr P2DIR  = 0xA6;
sfr P3DIR  = 0xA7;

sfr SP     = 0x81;

sfr DPL0   = 0x82;
sfr DPH0   = 0x83;

sfr DPL1   = 0x84;
sfr DPH1   = 0x85;

sfr DPS    = 0x86;

sfr PCON   = 0x87;
sfr TCON   = 0x88;
sfr TMOD   = 0x89;
sfr TL0    = 0x8A;
sfr TL1    = 0x8B;
sfr TH0    = 0x8C;
sfr TH1    = 0x8D;
sfr CKCON  = 0x8E;

sfr EXIF   = 0x91;
sfr MPAGE  = 0x92;
sfr SCON0  = 0x98;
sfr SBUF0  = 0x99;
sfr IE     = 0xA8;
sfr IP     = 0xB8;


sfr SCON1  = 0xC0;
sfr SBUF1  = 0xC1;

sfr PSW    = 0xD0;

sfr EICON  = 0xD8;
sfr EIE    = 0xE8;
sfr B      = 0xF0;
sfr EIP    = 0xF8;

sfr RANCON = 0xC7;
sfr RDATA  = 0xB9;
sfr RADRL  = 0xBA;
sfr RADRH  = 0xBB;

sfr PRESCALER   = 0xE6;
sfr RESERVED    = 0xE7;


/******  BIT accessible Registers ******/
/*P0*/
sbit P0_0  = P0^0;
sbit P0_1  = P0^1;
sbit P0_2  = P0^2;
sbit P0_3  = P0^3;

sbit MI    = P0^2;
sbit MO    = P0^1;
sbit SCK   = P0^0;

/*P1*/
sbit P1_0  = P1^0;
sbit P1_1  = P1^1;
sbit P1_2  = P1^2;
sbit P1_3  = P1^3;
sbit P1_4  = P1^4;
sbit P1_5  = P1^5;
sbit P1_6  = P1^6;
sbit P1_7  = P1^7;


/*P2*/
sbit P2_0  = P2^0;
sbit P2_1  = P2^1;
sbit P2_2  = P2^2;
sbit P2_3  = P2^3;
sbit P2_4  = P2^4;
sbit P2_5  = P2^5;
sbit P2_6  = P2^6;
sbit P2_7  = P2^7;

sbit RXD1  = P2^0;
sbit TXD1  = P2^1;
sbit ZEROX = P2^2;
sbit TRIAC = P2^3;

/*P3 */
sbit P3_0  = P3^0;
sbit P3_1  = P3^1;
sbit P3_2  = P3^2;
sbit P3_3  = P3^3;
sbit P3_4  = P3^4;
sbit P3_5  = P3^5;

sbit RXD0   = P3^0;
sbit TXD0   = P3^1;
sbit INT0_N = P3^2;
sbit INT1_N = P3^3;
sbit T0     = P3^4;
sbit T1     = P3^5;


/*  TCON  */
sbit TF1   = TCON^7;
sbit TR1   = TCON^6;
sbit TF0   = TCON^5;
sbit TR0   = TCON^4;
sbit IE1   = TCON^3;
sbit IT1   = TCON^2;
sbit IE0   = TCON^1;
sbit IT0   = TCON^0;

/*  SCON0  */
sbit SM0_0 = SCON0^7; 
sbit SM1_0 = SCON0^6; 
sbit SM2_0 = SCON0^5; 
sbit REN_0 = SCON0^4; 
sbit TB8_0 = SCON0^3; 
sbit RB8_0 = SCON0^2; 
sbit TI_0  = SCON0^1; 
sbit RI_0  = SCON0^0; 

/*  SCON1  */
sbit SM0_1 = SCON1^7; 
sbit SM1_1 = SCON1^6; 
sbit SM2_1 = SCON1^5; 
sbit REN_1 = SCON1^4; 
sbit TB8_1 = SCON1^3; 
sbit RB8_1 = SCON1^2; 
sbit TI_1  = SCON1^1; 
sbit RI_1  = SCON1^0; 

/*IE*/
sbit EA    = IE^7;
sbit ES1   = IE^6;
sbit ES0   = IE^4;
sbit ET1   = IE^3;
sbit EX1   = IE^2;
sbit ET0   = IE^1;
sbit EX0   = IE^0;

/*IP*/
sbit PS1   = IP^6;
sbit PS0   = IP^4;
sbit PT1   = IP^3;
sbit PX1   = IP^2;
sbit PT0   = IP^1;
sbit PX0   = IP^0;


/*RFMAIN*/
sbit RXTX    = RFMAIN^7; /*RX/TX switch*/
sbit F_REG   = RFMAIN^6; /*Select the freq registers A or B*/
sbit RX_PD   = RFMAIN^5; /*Select Pwr down for LDA, Mixer, IF, Demulator, RX part of signal interface*/
sbit TX_PD   = RFMAIN^4; /*Select Pwr down for TX part of signal interface and PA*/
sbit FS_PD   = RFMAIN^3; /*Select Pwr down of freq syntesiser*/
sbit CORE_PD = RFMAIN^2; /*Power down main xtal osc core*/
sbit BIAS_PD = RFMAIN^1;  /* Power down bias current generator and xtal osc buffer*/


/*PSW*/
/*  PSW */
sbit CY    = PSW^7;
sbit AC    = PSW^6;
sbit F0    = PSW^5;
sbit RS1   = PSW^4;
sbit RS0   = PSW^3;
sbit OV    = PSW^2;
sbit FL    = PSW^1;
sbit P     = PSW^0;

/*EICON*/
sbit SMOD1 = EICON^7;
sbit FDIE  = EICON^5;
sbit FDIF  = EICON^4;
sbit RTCIF = EICON^3;

/*ACC*/

/*EIE*/
sbit RTCIE   = EIE^4;
sbit ET3     = EIE^3;
sbit ADIE    = EIE^2;
sbit ET2     = EIE^1;
sbit RFIE    = EIE^0;

/*B*/


/*EIP*/
sbit PRTC    = EIP^4;
sbit PT3     = EIP^3;
sbit PAD     = EIP^2;
sbit PT2     = EIP^1;
sbit PRF     = EIP^0;


/****Common 8051 SFR registers not previously defined****/
/*  BYTE Register  */
sfr DPL  = 0x82;
sfr DPH  = 0x83;
sfr SCON = 0x98;
sfr SBUF = 0x99;

/*  BIT Register  */
/*  IE   */
sbit ES   = 0xAC;

/*  IP   */ 
sbit PS   = 0xBC;

/*  P3  */
sbit INT1 = 0xB3;
sbit INT0 = 0xB2;
sbit TXD  = 0xB1;
sbit RXD  = 0xB0;

/*  SCON  */
sbit SM0  = 0x9F;
sbit SM1  = 0x9E;
sbit SM2  = 0x9D;
sbit REN  = 0x9C;
sbit TB8  = 0x9B;
sbit RB8  = 0x9A;
sbit TI   = 0x99;
sbit RI   = 0x98;

// ************************* ISR vector addresses ****************************
// Usage example:
//      void my_serial_isr() interrupt INUM_UART0 {
//          ...
//      }

//INUM servicing FLASH DMA write finished / in-circuit debugger (opcode=0xA5)
#define INUM_FLASH      6

//ISR servicing external interrupt 0
#define INUM_INT0       0
#define INUM_EXTERNAL0  0

//ISR servicing timer 0
#define INUM_TIMER0     1

//ISR servicing external interrupt 1
#define INUM_INT1       2
#define INUM_EXTERNAL1  2

//ISR servicing timer 1
#define INUM_TIMER1     3

//ISR servicing serial port 0
#define INUM_SERIAL0    4
#define INUM_UART0      4
#define INUM_UART0_RX   40             // Can not be an ISR
#define INUM_UART0_TX   41             // Can not be an ISR

//ISR servicing serial port 1
#define INUM_SERIAL1    7
#define INUM_UART1      7
#define INUM_UART1_RX   70             // Can not be an ISR
#define INUM_UART1_TX   71             // Can not be an ISR

//ISR servicing RF receive/transmit
#define INUM_RF         8

//ISR servicing timer 2
#define INUM_TIMER2     9

//ISR servicing DES module / ADC 
#define INUM_DES_ADC    10
#define INUM_DES        100             // Can not be an ISR
#define INUM_ADC        101             // Can not be an ISR

//ISR servicing timer 3
#define INUM_TIMER3     11

//ISR servicing Realtime clock
#define INUM_RTC        12

#endif //REG1010_H
#endif /*If not WIN32*/