pciConfigInWord (pciBusLpc, pciDevLpc, pciFuncLpc, 	PCI_CFG_DEVICE_ID, &deviceId);    if (!(((vendorId == ICH2_LPC_VID) &&           ((deviceId == ICH2_LPC_DID_S) || (deviceId == ICH2_LPC_DID_M))) ||          ((vendorId == ICH3_LPC_VID) &&           ((deviceId == ICH3_LPC_DID_S) || (deviceId == ICH3_LPC_DID_M)))))       return;    /* enables or disables 1) IOAPIC address decode 2) IO XAPIC extensions */    pciConfigInLong (pciBusLpc, pciDevLpc, pciFuncLpc, 	ICH2_LPC_GEN_CNTL, &value);    if (enable)        value |= (ICH2_APICEN | ICH2_XAPIC_EN);    else        value &= ~(ICH2_APICEN | ICH2_XAPIC_EN);    pciConfigOutLong (pciBusLpc, pciDevLpc, pciFuncLpc, 	ICH2_LPC_GEN_CNTL, value);#endif	/* defined (INCLUDE_ICH2) || defined (INCLUDE_ICH3) */    }/************************************************************************* sysPciPirqEnable - enable or disbale PCI PIRQ direct handling ** This routine enables or disbales the PCI PIRQ direct handling.* This routine is called by ioApicEnable() in the SYMMETRIC IO mode.** RETURNS: N/A*/VOID sysPciPirqEnable     (    BOOL enable		/* TRUE to enable, FALSE to disable */    )    {    static BOOL sysPciFirstTime = TRUE;    if (sysPciFirstTime)        {#   if defined (INCLUDE_ICH2) || defined (INCLUDE_ICH3)        {        INT32 pciBusLpc	 = ICH2_LPC_PCI_BUSNO;        INT32 pciDevLpc	 = ICH2_LPC_PCI_DEVNO;        INT32 pciFuncLpc = ICH2_LPC_PCI_FUNCNO;        INT32 pirq;        UINT8 irq;        /* saves the default PIRQ[A-H] routing info */        for (pirq = 0; pirq < N_IOAPIC_PIRQS; pirq++)	    {	    pciConfigInByte (pciBusLpc, pciDevLpc, pciFuncLpc,	        sysPciPirqTbl[pirq].offset, &irq);	    sysPciPirqTbl[pirq].irq = (irq & ~ICH2_IRQ_DIS);	    }        }#   endif /* defined (INCLUDE_ICH2) || defined (INCLUDE_ICH3) */#   ifdef INCLUDE_UNKNOWN_MOTHER	{        INT32  pciBus;        INT32  pciDev;        UINT16 vendorId;        UINT16 deviceId;        UINT8  classCode;        UINT8  intPin;        UINT8  intLine;        INT32  ix;        /* collect the PCI network device info */        ix = 0;        for (pciBus = 0; pciBus < PCI_MAX_BUS; pciBus++)	    {	    for (pciDev = 0; pciDev < PCI_MAX_DEV; pciDev++)	        {		/* just PCI function 0 for now */	        pciConfigInWord (pciBus, pciDev, 0, PCI_CFG_VENDOR_ID, 		    &vendorId);                pciConfigInWord (pciBus, pciDev, 0, PCI_CFG_DEVICE_ID, 		    &deviceId);                pciConfigInByte (pciBus, pciDev, 0, PCI_CFG_CLASS, 		    &classCode);                pciConfigInByte (pciBus, pciDev, 0, PCI_CFG_DEV_INT_PIN, 		    &intPin);                pciConfigInByte (pciBus, pciDev, 0, PCI_CFG_DEV_INT_LINE, 		    &intLine);	    	        /* just PCI network card for now */	        if ((vendorId != 0xffff) && (classCode == 0x2))	            {	            if (ix < N_PCI_NETS)	                {	                sysPciNetTbl[ix].pciBus    = pciBus;	                sysPciNetTbl[ix].pciDev    = pciDev;	                sysPciNetTbl[ix].pciFunc   = 0;	                sysPciNetTbl[ix].vendorId  = vendorId;	                sysPciNetTbl[ix].deviceId  = deviceId;	                sysPciNetTbl[ix].classCode = classCode;	                sysPciNetTbl[ix].intPin    = intPin;	                sysPciNetTbl[ix].intLine   = intLine;	                ix++;	    	        }	            sysPciNnets++;	            }    	        }    	    }    	}#   endif /* INCLUDE_UNKNOWN_MOTHER */        sysPciFirstTime = FALSE;        }    /* enables or disables the PIRQ direct handling */#   if defined (INCLUDE_ICH2) || defined (INCLUDE_ICH3)    {    INT32 pciBusLpc  = ICH2_LPC_PCI_BUSNO;    INT32 pciDevLpc  = ICH2_LPC_PCI_DEVNO;    INT32 pciFuncLpc = ICH2_LPC_PCI_FUNCNO;    INT32 pirq;    for (pirq = 0; pirq < N_IOAPIC_PIRQS; pirq++)	{	if (enable)	    {	    pciConfigOutByte (pciBusLpc, pciDevLpc, pciFuncLpc,	        sysPciPirqTbl[pirq].offset, 		(sysPciPirqTbl[pirq].irq | ICH2_IRQ_DIS));	    }	else	    {	    pciConfigOutByte (pciBusLpc, pciDevLpc, pciFuncLpc,	        sysPciPirqTbl[pirq].offset, 		(sysPciPirqTbl[pirq].irq & ~ICH2_IRQ_DIS));	    }	}    }#   endif /* defined (INCLUDE_ICH2) || defined (INCLUDE_ICH3) */    /* set the PIRQ[A-H] to PCI_CFG_DEV_INT_LINE for direct handling */#   ifdef INCLUDE_UNKNOWN_MOTHER    {    INT32 ix;    if (enable)	{        /* 	 * INT_LINE should have IRQ number of PIRQ[A-H] (16 - 23).	 * Since INT[A-D] to PIRQ[A-H] wiring info is unknown, value to set	 * is unknown too.  So set PIRQA to PCI_CFG_DEV_INT_LINE for now.	 * Note, setting PIRQA does not mean the device generates PIRQA.	 */        for (ix = 0; ix < sysPciNnets; ix++)            {	    pciConfigOutByte (sysPciNetTbl[ix].pciBus, sysPciNetTbl[ix].pciDev, 		sysPciNetTbl[ix].pciFunc, PCI_CFG_DEV_INT_LINE, 		IOAPIC_PIRQA_INT_LVL);            }	}    else	{        /* restore the original IRQn to PCI_CFG_DEV_INT_LINE */        for (ix = 0; ix < sysPciNnets; ix++)            {	    pciConfigOutByte (sysPciNetTbl[ix].pciBus, sysPciNetTbl[ix].pciDev, 		sysPciNetTbl[ix].pciFunc, PCI_CFG_DEV_INT_LINE, 		sysPciNetTbl[ix].intLine);            }	}    }#   elif defined (INCLUDE_D815EEA) || defined (INCLUDE_D850GB)    {    INT32 pciBusSlot	= MOTHER_PCI_BUSNO_SLOT;    INT32 pciFuncSlot	= MOTHER_PCI_FUNCNO_SLOT;    INT32 pciBusLpc	= ICH2_LPC_PCI_BUSNO;    INT32 pciDevLpc	= ICH2_LPC_PCI_DEVNO;    INT32 pciFuncLpc	= ICH2_LPC_PCI_FUNCNO;    UINT8 intPin;	/* PCI INT[A-D] from PCI Int Pin Reg */    UINT8 irq;		/* IRQ[0-15] of the device */    INT32 vendorId;	/* PCI vendor Id */    INT32 pirq;    UINT32 index;    INT32 ix;    for (ix = 0; ix < N_PCI_SLOTS; ix++)	{	/* skip if the slot is empty */        pciConfigInLong (pciBusSlot, sysPciSlotTbl[ix], pciFuncSlot, 	    PCI_CFG_VENDOR_ID, &vendorId);	if ((vendorId & 0x0000ffff) == 0x0000ffff)	    continue;	/* get the PCI INT[A-D] of the device */        pciConfigInByte (pciBusSlot, sysPciSlotTbl[ix], pciFuncSlot, 	    PCI_CFG_DEV_INT_PIN, &intPin);	/* get the PIRQ[A-H] */	pirq = sysPciIntTbl[ix][intPin - 1];	/* get the original IRQ[0-15] */	index = pirq - IOAPIC_PIRQA_INT_LVL;	irq   = sysPciPirqTbl[index].irq;        if (enable)            {	    /* set the PIRQ[A-H] to the PCI_CFG_DEV_INT_LINE */            pciConfigOutByte (pciBusSlot, sysPciSlotTbl[ix], pciFuncSlot, 		PCI_CFG_DEV_INT_LINE, pirq);	    }        else	    {            /* restore the original IRQ[0-15] to PCI_CFG_DEV_INT_LINE */            pciConfigOutByte (pciBusSlot, sysPciSlotTbl[ix], pciFuncSlot, 	        PCI_CFG_DEV_INT_LINE, irq);	    }	}    }#   endif /* INCLUDE_UNKNOWN_MOTHER */    }#ifdef	INCLUDE_SHOW_ROUTINES/********************************************************************************* sysPciPirqShow - show the PCI PIRQ[A-H] to IRQ[0-15] routing status** This routine shows the PCI PIRQ[A-H] to IRQ[0-15] routing status** RETURNS: N/A*/void sysPciPirqShow (void)    {#   if defined (INCLUDE_ICH2) || defined (INCLUDE_ICH3)    {    INT32 ix;    /* show the PIRQ[A-H] - IRQ[0-15] routing table */    for (ix = 0; ix < N_IOAPIC_PIRQS; ix++)	{        printf ("PIRQ%c: offset=0x%04x, PIRQ=0x%02x, IRQ=0x%02x\n",	    'A' + ix,            sysPciPirqTbl[ix].offset,            sysPciPirqTbl[ix].pirq,            sysPciPirqTbl[ix].irq);	}    }#   endif /* defined (INCLUDE_ICH2) || defined (INCLUDE_ICH3) */#   ifdef INCLUDE_UNKNOWN_MOTHER    {    INT32 ix;    /* show the network device table */    for (ix = 0; ix < sysPciNnets; ix++)	{        printf ("bus=0x%04x dev=0x%04x venId=0x%04x "            "devId=0x%04x intPin=0x%02x intLine=0x%02x\n",            sysPciNetTbl[ix].pciBus,            sysPciNetTbl[ix].pciDev,            sysPciNetTbl[ix].vendorId,            sysPciNetTbl[ix].deviceId,            sysPciNetTbl[ix].intPin,            sysPciNetTbl[ix].intLine);	}    }#   elif defined (INCLUDE_D815EEA) || defined (INCLUDE_D850GB)    {    INT32 pciBusSlot	= MOTHER_PCI_BUSNO_SLOT;    INT32 pciFuncSlot	= MOTHER_PCI_FUNCNO_SLOT;    FUNCPTR defIsr;	/* ISR of the default IRQ */    FUNCPTR curIsr;	/* ISR of the current IRQ */    INT32 idtType;	/* IDT type */    INT32 selector;	/* CS selector */    INT32 vendorId;	/* PCI vendor Id */    UINT8 intPin;	/* PCI INT[A-D] from PCI Int Pin Reg */    UINT8 defIrq;	/* default IRQ */    UINT8 curIrq;	/* current IRQ */    UINT8 pirq;		/* PIRQ[n] */    INT32 ix;    for (ix = 0; ix < N_PCI_SLOTS; ix++)	{	/* skip if the slot is empty */        pciConfigInLong (pciBusSlot, sysPciSlotTbl[ix], pciFuncSlot, 			 PCI_CFG_VENDOR_ID, &vendorId);	if ((vendorId & 0x0000ffff) == 0x0000ffff)	    {	    printf ("slot %d: empty \n", ix);	    continue;	    }	/* get the PCI INT[A-D] and IRQ[0-15] of the device */        pciConfigInByte (pciBusSlot, sysPciSlotTbl[ix], pciFuncSlot, 	    PCI_CFG_DEV_INT_PIN, &intPin);        pciConfigInByte (pciBusSlot, sysPciSlotTbl[ix], pciFuncSlot, 	    PCI_CFG_DEV_INT_LINE, &curIrq);	/* get the PIRQ[A-H] of the device */	pirq = sysPciIntTbl[ix][intPin - 1];	/* if sysPciPirqTbl[] table is not initialized, use the curIrq */	defIrq = sysPciPirqTbl[pirq - IOAPIC_PIRQA_INT_LVL].irq; 	/* get the default Isr and current Isr */	intVecGet2 ((FUNCPTR *)INUM_TO_IVEC (INT_NUM_GET (defIrq)), 	    &defIsr, &idtType, &selector);	intVecGet2 ((FUNCPTR *)INUM_TO_IVEC (INT_NUM_GET (curIrq)), 	    &curIsr, &idtType, &selector);	/* show the default IRQ and the current IRQ setting */	printf ("slot %d: def-IRQ(ISR) = 0x%04x(0x%08x)  "		"cur-IRQ(ISR) = 0x%04x(0x%08x)\n",		ix, defIrq, (int)defIsr, curIrq, (int)curIsr);	}    }#   endif /* INCLUDE_UNKNOWN_MOTHER */    }#endif	/* INCLUDE_SHOW_ROUTINES */#endif	/* SYMMETRIC_IO_MODE */