?? pll.asm
字號:
;******************************************************************************
;* TMS320C6x C/C++ Codegen PC Version 4.32 *
;* Date/Time created: Mon Oct 22 22:26:24 2007 *
;******************************************************************************
;******************************************************************************
;* GLOBAL FILE PARAMETERS *
;* *
;* Architecture : TMS320C671x *
;* Optimization : Enabled at level 3 *
;* Optimizing for : Speed 1st, size 2nd *
;* Based on options: -o3, -ms0 *
;* Endian : Little *
;* Interrupt Thrshld : Disabled *
;* Memory Model : Small *
;* Calls to RTS : Far *
;* Pipelining : Enabled *
;* Speculative Load : Disabled *
;* Memory Aliases : Presume not aliases (optimistic) *
;* Debug Info : COFF Debug *
;* *
;******************************************************************************
.asg A15, FP
.asg B14, DP
.asg B15, SP
.global $bss
.file "pll.c"
; c:\ti6000\c6000\cgtools\bin\opt6x.exe -t -v6710 -q -O3 -Z0 C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\TI944_2 C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\TI944_5 -w E:/work/tms6713 sell board data/DSPSRC/Audiocfg_IIR/Debug
.sect ".text"
.global _plldelay
.sym _plldelay,_plldelay, 32, 2, 0
.func 17
;----------------------------------------------------------------------
; 17 | void plldelay(unsigned int delaynum)
;----------------------------------------------------------------------
;******************************************************************************
;* FUNCTION NAME: _plldelay *
;* *
;* Regs Modified : *
;* Regs Used : B3 *
;* Local Frame Size : 0 Args + 0 Auto + 0 Save = 0 byte *
;******************************************************************************
;******************************************************************************
;* *
;* Using -g (debug) with optimization (-o3) may disable key optimizations! *
;* *
;******************************************************************************
_plldelay:
;** --------------------------------------------------------------------------*
.line 2
.sym _delaynum,4, 14, 17, 32
.sym _delaynum,0, 14, 4, 32
;----------------------------------------------------------------------
; 19 | unsigned int i=delaynum;
;----------------------------------------------------------------------
.line 4
;----------------------------------------------------------------------
; 20 | while(i--);
;----------------------------------------------------------------------
.line 5
RET .S2 B3 ; |21|
NOP 5
; BRANCH OCCURS ; |21|
.endfunc 21,000000000h,0
.sect ".text"
.global _PLLInit
.sym _PLLInit,_PLLInit, 32, 2, 0
.func 22
;----------------------------------------------------------------------
; 22 | void PLLInit(void)
;----------------------------------------------------------------------
;******************************************************************************
;* FUNCTION NAME: _PLLInit *
;* *
;* Regs Modified : A0,A3,B4,B5 *
;* Regs Used : A0,A3,B3,B4,B5 *
;* Local Frame Size : 0 Args + 0 Auto + 0 Save = 0 byte *
;******************************************************************************
;******************************************************************************
;* *
;* Using -g (debug) with optimization (-o3) may disable key optimizations! *
;* *
;******************************************************************************
_PLLInit:
;** --------------------------------------------------------------------------*
.line 2
.line 3
;----------------------------------------------------------------------
; 24 | *(volatile unsigned int *)PLLCSR &=~CSR_PLLEN;/*disable the PLL,in bypa
; | ss status*/
; 25 | plldelay(20);
;----------------------------------------------------------------------
MVKL .S2 0x1b7c100,B4 ; |24|
MVKH .S2 0x1b7c100,B4 ; |24|
LDW .D2T2 *B4,B5 ; |24|
NOP 4
AND .S2 -2,B5,B5 ; |24|
STW .D2T2 B5,*B4 ; |24|
.line 5
;----------------------------------------------------------------------
; 26 | *(volatile unsigned int *)PLLCSR |=CSR_PLLRST;/*PLL in the reset Status
; | */
; 27 | plldelay(20);
;----------------------------------------------------------------------
MVKL .S1 0x1b7c100,A0 ; |26|
MVKH .S1 0x1b7c100,A0 ; |26|
LDW .D1T1 *A0,A3 ; |26|
NOP 4
OR .S1 8,A3,A3 ; |26|
STW .D1T1 A3,*A0 ; |26|
.line 7
;----------------------------------------------------------------------
; 28 | *(volatile unsigned int *)PLLDIV0=DIV_ENABLE;/*divide 1,output the same
; | frequence*/
;----------------------------------------------------------------------
MVKL .S2 0x1b7c114,B5 ; |28|
MVKH .S2 0x1b7c114,B5 ; |28|
|| ZERO .D2 B4 ; |28|
SET .S2 B4,0xf,0xf,B4 ; |28|
STW .D2T2 B4,*B5 ; |28|
.line 8
;----------------------------------------------------------------------
; 29 | *(volatile unsigned int *)PLLMULT=17;/*Multiply 17 and the pll frequenc
; | e is 208Mhz */
;----------------------------------------------------------------------
MVKL .S1 0x1b7c110,A0 ; |29|
MVKH .S1 0x1b7c110,A0 ; |29|
|| MVK .S2 17,B5 ; |29|
STW .D1T2 B5,*A0 ; |29|
.line 10
;----------------------------------------------------------------------
; 31 | *(volatile unsigned int *)PLLOSCDIV1=DIV_ENABLE+0;/*clkout 3 output,10M
; | Hz*/
;----------------------------------------------------------------------
MVKL .S2 0x1b7c124,B5 ; |31|
MVKH .S2 0x1b7c124,B5 ; |31|
STW .D2T2 B4,*B5 ; |31|
.line 11
;----------------------------------------------------------------------
; 32 | *(volatile unsigned int *)PLLDIV3=DIV_ENABLE+1;/*208Mhz/2=104Mhz for th
; | e EMIF port*/
;----------------------------------------------------------------------
MVKL .S1 0x1b7c120,A3 ; |32|
MVK .S1 32767,A0 ; |32|
ADD .D1 0x2,A0,A0 ; |32|
|| MVKH .S1 0x1b7c120,A3 ; |32|
STW .D1T1 A0,*A3 ; |32|
.line 12
;----------------------------------------------------------------------
; 33 | *(volatile unsigned int *)PLLDIV2=DIV_ENABLE+1;/*208Mhz/2=104Mhz for Pe
; | ripherals */
;----------------------------------------------------------------------
MVKL .S2 0x1b7c11c,B5 ; |33|
MVKH .S2 0x1b7c11c,B5 ; |33|
STW .D2T1 A0,*B5 ; |33|
.line 13
;----------------------------------------------------------------------
; 34 | *(volatile unsigned int *)PLLDIV1=DIV_ENABLE+0;/*208Mhz for cpu core fr
; | equence*/
;----------------------------------------------------------------------
MVKL .S1 0x1b7c118,A0 ; |34|
MVKH .S1 0x1b7c118,A0 ; |34|
STW .D1T2 B4,*A0 ; |34|
.line 14
;----------------------------------------------------------------------
; 35 | *(volatile unsigned int *)PLLCSR &= ~CSR_PLLRST;/*Reset release*/
; 36 | plldelay(1500);
;----------------------------------------------------------------------
MVKL .S2 0x1b7c100,B4 ; |35|
MVKH .S2 0x1b7c100,B4 ; |35|
LDW .D2T2 *B4,B5 ; |35|
NOP 4
AND .S2 -9,B5,B5 ; |35|
STW .D2T2 B5,*B4 ; |35|
.line 16
;----------------------------------------------------------------------
; 37 | *(volatile unsigned int *)PLLCSR |=CSR_PLLEN;/*enable the PLL*/
;----------------------------------------------------------------------
MVKL .S1 0x1b7c100,A0 ; |37|
MVKH .S1 0x1b7c100,A0 ; |37|
LDW .D1T1 *A0,A3 ; |37|
NOP 4
OR .S1 1,A3,A3 ; |37|
STW .D1T1 A3,*A0 ; |37|
.line 17
;----------------------------------------------------------------------
; 38 | plldelay(20);
;----------------------------------------------------------------------
.line 18
RET .S2 B3 ; |39|
NOP 5
; BRANCH OCCURS ; |39|
.endfunc 39,000000000h,0
;******************************************************************************
;* TYPE INFORMATION *
;******************************************************************************
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