/*Define the PLL register*/
#define PLLCSR 0x01B7C100
#define PLLMULT 0x01B7C110
#define PLLDIV0 0x01B7C114
#define PLLDIV1 0x01B7C118
#define PLLDIV2 0x01B7C11C
#define PLLDIV3 0x01B7C120
#define PLLOSCDIV1 0x01B7C124 

#define CSR_PLLEN          0x00000001
#define CSR_PLLPWRDN       0x00000002
#define CSR_PLLRST         0x00000008 
#define CSR_PLLSTABLE      0x00000040

#define DIV_ENABLE         0x00008000

void plldelay(unsigned int delaynum)
  {
    unsigned int i=delaynum;
    while(i--);   
   }
void PLLInit(void)
  {
   *(volatile unsigned int *)PLLCSR &=~CSR_PLLEN;/*disable the PLL,in bypass status*/
   plldelay(20);
   *(volatile unsigned int *)PLLCSR |=CSR_PLLRST;/*PLL in the reset Status*/
   plldelay(20);
   *(volatile unsigned int *)PLLDIV0=DIV_ENABLE;/*divide 1,output the same frequence*/
   *(volatile unsigned int *)PLLMULT=17;/*Multiply 17 and the pll frequence is 208Mhz */
                                        /*12.288M*17=208M,其中12.288M是DSP的外部頻率*/
   *(volatile unsigned int *)PLLOSCDIV1=DIV_ENABLE+0;/*clkout 3 output,10MHz*/
   *(volatile unsigned int *)PLLDIV3=DIV_ENABLE+1;/*208Mhz/2=104Mhz for the EMIF port*/
   *(volatile unsigned int *)PLLDIV2=DIV_ENABLE+1;/*208Mhz/2=104Mhz for Peripherals */
   *(volatile unsigned int *)PLLDIV1=DIV_ENABLE+0;/*208Mhz for cpu core frequence*/
   *(volatile unsigned int *)PLLCSR &= ~CSR_PLLRST;/*Reset release*/
   plldelay(1500);
   *(volatile unsigned int *)PLLCSR |=CSR_PLLEN;/*enable the PLL*/
   plldelay(20);
   }