?? 91x_map.h
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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_map.h
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : Peripherals registers definition and memory mapping.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion ------------------------------------ */
#ifndef __91x_MAP_H
#define __91x_MAP_H
#ifndef EXT
#define EXT extern
#endif /* EXT */
/* Includes ------------------------------------------------------------------*/
#include "91x_conf.h"
#include "91x_type.h"
/******************************************************************************/
/* IP registers structures */
/******************************************************************************/
/*------------------------------------ FMI -----------------------------------*/
typedef struct
{
vu32 BBSR; /* Boot Bank Size Register */
vu32 NBBSR; /* Non-Boot Bank Size Register */
vu32 EMPTY1;
vu32 BBADR; /* Boot Bank Base Address Register */
vu32 NBBADR; /* Non-Boot Bank Base Address Register */
vu32 EMPTY2;
vu32 CR; /* Control Register */
vu32 SR; /* Status Register */
vu32 BCE5ADDR; /* BC Fifth Entry Target Address Register */
} FMI_TypeDef;
/*---------------------- Analog to Digital Convertor ------------------------*/
typedef struct
{
vu16 CR; /* Control Register */
vu16 EMPTY1;
vu16 CCR; /* Channel Configuration Register */
vu16 EMPTY2;
vu16 HTR; /* Higher Threshold Register */
vu16 EMPTY3;
vu16 LTR; /* Lower Threshold Register */
vu16 EMPTY4;
vu16 CRR; /* Compare Result Register */
vu16 EMPTY5;
vu16 DR0; /* Data Register for Channel 0 */
vu16 EMPTY6;
vu16 DR1; /* Data Register for Channel 1 */
vu16 EMPTY7;
vu16 DR2; /* Data Register for Channel 2 */
vu16 EMPTY8;
vu16 DR3; /* Data Register for Channel 3 */
vu16 EMPTY9;
vu16 DR4; /* Data Register for Channel 4 */
vu16 EMPTY10;
vu16 DR5; /* Data Register for Channel 5 */
vu16 EMPTY11;
vu16 DR6; /* Data Register for Channel 6 */
vu16 EMPTY12;
vu16 DR7; /* Data Register for Channel 7 */
vu16 EMPTY13;
vu16 PRS; /* Prescaler Value Register */
vu16 EMPTY14;
} ADC_TypeDef;
/*--------------------- AHB APB BRIDGE registers strcture --------------------*/
typedef struct
{
vu32 BSR; /* Bridge Status Register */
vu32 BCR; /* Bridge Configuration Register */
vu32 PAER; /* Peripheral Address Error register */
} AHBAPB_TypeDef;
/*--------------- Controller Area Network Interface Register -----------------*/
typedef struct
{
vu16 CRR; /* IFn Command request Register */
vu16 EMPTY1;
vu16 CMR; /* IFn Command Mask Register */
vu16 EMPTY2;
vu16 M1R; /* IFn Message Mask 1 Register */
vu16 EMPTY3;
vu16 M2R; /* IFn Message Mask 2 Register */
vu16 EMPTY4;
vu16 A1R; /* IFn Message Arbitration 1 Register */
vu16 EMPTY5;
vu16 A2R; /* IFn Message Arbitration 2 Register */
vu16 EMPTY6;
vu16 MCR; /* IFn Message Control Register */
vu16 EMPTY7;
vu16 DA1R; /* IFn DATA A 1 Register */
vu16 EMPTY8;
vu16 DA2R; /* IFn DATA A 2 Register */
vu16 EMPTY9;
vu16 DB1R; /* IFn DATA B 1 Register */
vu16 EMPTY10;
vu16 DB2R; /* IFn DATA B 2 Register */
vu16 EMPTY11[27];
} CAN_MsgObj_TypeDef;
typedef struct
{
vu16 CR; /* Control Register */
vu16 EMPTY1;
vu16 SR; /* Status Register */
vu16 EMPTY2;
vu16 ERR; /* Error counter Register */
vu16 EMPTY3;
vu16 BTR; /* Bit Timing Register */
vu16 EMPTY4;
vu16 IDR; /* Interrupt Identifier Register */
vu16 EMPTY5;
vu16 TESTR; /* Test Register */
vu16 EMPTY6;
vu16 BRPR; /* BRP Extension Register */
vu16 EMPTY7[3];
CAN_MsgObj_TypeDef sMsgObj[2];
vu16 EMPTY8[16];
vu16 TXR1R; /* Transmission request 1 Register */
vu16 EMPTY9;
vu16 TXR2R; /* Transmission Request 2 Register */
vu16 EMPTY10[13];
vu16 ND1R; /* New Data 1 Register */
vu16 EMPTY11;
vu16 ND2R; /* New Data 2 Register */
vu16 EMPTY12[13];
vu16 IP1R; /* Interrupt Pending 1 Register */
vu16 EMPTY13;
vu16 IP2R; /* Interrupt Pending 2 Register */
vu16 EMPTY14[13];
vu16 MV1R; /* Message Valid 1 Register */
vu16 EMPTY15;
vu16 MV2R; /* Message VAlid 2 Register */
vu16 EMPTY16;
} CAN_TypeDef;
/*----------------------- System Control Unit---------------------------------*/
typedef struct
{
vu32 CLKCNTR; /* Clock Control Register */
vu32 PLLCONF; /* PLL Configuration Register */
vu32 SYSSTATUS; /* System Status Register */
vu32 PWRMNG; /* Power Management Register */
vu32 ITCMSK; /* Interrupt Mask Register */
vu32 PCGRO; /* Peripheral Clock Gating Register 0 */
vu32 PCGR1; /* Peripheral Clock Gating Register 1 */
vu32 PRR0; /* Peripheral Reset Register 0 */
vu32 PRR1; /* Peripheral Reset Register 1 */
vu32 MGR0; /* Idle Mode Mask Gating Register 0 */
vu32 MGR1; /* Idle Mode Mask Gating Register 1 */
vu32 PECGR0; /* Peripheral Emulation Clock Gating Register 0 */
vu32 PECGR1; /* Peripheral Emulation Clock Gating Register 1 */
vu32 SCR0; /* System Configuration Register 0 */
vu32 SCR1; /* System Configuration Register 1 */
vu32 SCR2; /* System Configuration Register 2 */
u32 EMPTY1;
vu32 GPIOOUT[8]; /* GPIO Output Registers */
vu32 GPIOIN[8]; /* GPIO Input Registers */
vu32 GPIOTYPE[10]; /* GPIO Type Registers */
vu32 GPIOEMI; /* GPIO EMI Selector Register */
vu32 WKUPSEL; /* Wake-Up Selection Register */
u32 EMPTY2[2];
vu32 GPIOANA; /* GPIO Analag mode Register */
} SCU_TypeDef;
/*------------------------- DMA Channelx Registers ---------------------------*/
typedef struct
{
vu32 SRC; /* Channelx Source Address Register */
vu32 DES; /* Channelx Destination Address Register */
vu32 LLI; /* Channelx Lincked List Item Register */
vu32 CC; /* Channelx Contol Register */
vu32 CCNF; /* Channelx Configuration Register */
} DMA_Channel_TypeDef;
/* x can be ,0,1,2,3,4,5,6 or 7. There are eight Channels AHB BUS Master */
/*----------------------------- DMA Controller -------------------------------*/
typedef struct
{
vu32 ISR; /* Interrupt Status Register */
vu32 TCISR; /* Terminal Count Interrupt Status Register */
vu32 TCICR; /* Terminal CountInterrupt Clear Register */
vu32 EISR; /* Error Interrupt Status Register */
vu32 EICR; /* Error Interrupt Clear Register */
vu32 TCRISR; /* Terminal Count Raw Interrupt Status Register */
vu32 ERISR; /* Raw Error Interrupt Status Register */
vu32 ENCSR; /* Enabled Channel Status Register */
vu32 SBRR; /* Software Burst Request Register */
vu32 SSRR; /* Software Single Request Register */
vu32 SLBRR; /* Software Last Burst Request Register */
vu32 SLSRR; /* Software Last Single Request Register */
vu32 CNFR; /* Configuration Register */
vu32 SYNR; /* Syncronization Register */
} DMA_TypeDef;
/*--------------------------------- TIM Timer --------------------------------*/
typedef struct
{
vu16 IC1R; /* Input Capture 1 Register */
vu16 EMPTY1;
vu16 IC2R; /* Input Capture 2 Register */
vu16 EMPTY2;
vu16 OC1R; /* Output Compare 1 Register */
vu16 EMPTY3;
vu16 OC2R; /* Output Compare 2 Register */
vu16 EMPTY4;
vu16 CNTR; /* Counter Register */
vu16 EMPTY5;
vu16 CR1; /* Control Register 1 */
vu16 EMPTY6;
vu16 CR2; /* Control Register 2 */
vu16 EMPTY7;
vu16 SR; /* Status Register */
vu16 EMPTY8;
} TIM_TypeDef;
/*---------------------------- EMI Bankx Registers ---------------------------*/
typedef struct
{
vu32 ICR; /* Bankx Idle Cycle Control Register */
vu32 RCR; /* Bankx Read Wait State Control Register */
vu32 WCR; /* Bankx Write Wait State Control Register */
vu32 OECR; /* Bankx Output Enable Assertion Delay Control Register */
vu32 WECR; /* Bankx Write Enable Assertion Delay Control Register */
vu32 BCR; /* Bankx Control Register */
} EMI_Bank_TypeDef;
/*---------------------------- Ethernet Controller ---------------------------*/
/* MAC Registers */
typedef struct
{
vu32 MCR; /* ENET Control Register */
vu32 MAH; /* ENET Address High Register */
vu32 MAL; /* ENET Address Low Register */
vu32 MCHA; /* Multicast Address High Register */
vu32 MCLA; /* Multicast Address Low Register */
vu32 MIIA; /* MII Address Register */
vu32 MIID; /* MII Data Register */
vu32 MCF; /* ENET Control Frame Register */
vu32 VL1; /* VLAN1 Register */
vu32 VL2; /* VLAN2 register */
vu32 MTS; /* ENET Transmission Status Register */
vu32 MRS; /* ENET Reception Status Register */
} ENET_MAC_TypeDef;
/* DMA Registers */
typedef struct
{
vu32 SCR; /* DMA Status and Control Register */
vu32 IER; /* DMA Interrupt Sources Enable Register */
vu32 ISR; /* DMA Interrupt Status Register */
vu32 CCR; /* Clock Control Relation : HCLK, PCLK and
ENET_CLK phase relations */
vu32 RXSTR; /* Rx DMA start Register */
vu32 RXCR; /* Rx DMA Control Register */
vu32 RXSAR; /* Rx DMA Base Address Register */
vu32 RXNDAR; /* Rx DMA Next Descriptor Address Register */
vu32 RXCAR; /* Rx DMA Current Address Register */
vu32 RXCTCR; /* Rx DMA Current Transfer Count Register */
vu32 RXTOR; /* Rx DMA FIFO Time Out Register */
vu32 RXSR; /* Rx DMA FIFO Status Register */
vu32 TXSTR; /* Tx DMA start Register */
vu32 TXCR; /* Tx DMA Control Register */
vu32 TXSAR; /* Tx DMA Base Address Register */
vu32 TXNDAR; /* Tx DMA Next Descriptor Address Register */
vu32 TXCAR; /* Tx DMA Current Address Register */
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