?? pcm_bianma.mdl
字號:
Model {
Name "pcm_bianma"
Version 5.0
SaveDefaultBlockParams on
SampleTimeColors off
LibraryLinkDisplay "none"
WideLines off
ShowLineDimensions off
ShowPortDataTypes off
ShowLoopsOnError on
IgnoreBidirectionalLines off
ShowStorageClass off
ExecutionOrder off
RecordCoverage off
CovPath "/"
CovSaveName "covdata"
CovMetricSettings "dw"
CovNameIncrementing off
CovHtmlReporting on
covSaveCumulativeToWorkspaceVar on
CovSaveSingleToWorkspaceVar on
CovCumulativeVarName "covCumulativeData"
CovCumulativeReport off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
MinMaxOverflowArchiveMode "Overwrite"
BlockNameDataTip off
BlockParametersDataTip off
BlockDescriptionStringDataTip off
ToolBar on
StatusBar on
BrowserShowLibraryLinks off
BrowserLookUnderMasks off
Created "Tue Apr 27 18:47:48 2004"
UpdateHistory "UpdateHistoryNever"
ModifiedByFormat "%<Auto>"
LastModifiedBy "aa"
ModifiedDateFormat "%<Auto>"
LastModifiedDate "Wed Apr 28 14:03:05 2004"
ModelVersionFormat "1.%<AutoIncrement:5>"
ConfigurationManager "None"
SimParamPage "Solver"
LinearizationMsg "none"
Profile off
ParamWorkspaceSource "MATLABWorkspace"
AccelSystemTargetFile "accel.tlc"
AccelTemplateMakefile "accel_default_tmf"
AccelMakeCommand "make_rtw"
TryForcingSFcnDF off
ExtModeMexFile "ext_comm"
ExtModeBatchMode off
ExtModeTrigType "manual"
ExtModeTrigMode "normal"
ExtModeTrigPort "1"
ExtModeTrigElement "any"
ExtModeTrigDuration 1000
ExtModeTrigHoldOff 0
ExtModeTrigDelay 0
ExtModeTrigDirection "rising"
ExtModeTrigLevel 0
ExtModeArchiveMode "off"
ExtModeAutoIncOneShot off
ExtModeIncDirWhenArm off
ExtModeAddSuffixToVar off
ExtModeWriteAllDataToWs off
ExtModeArmWhenConnect on
ExtModeSkipDownloadWhenConnect off
ExtModeLogAll on
ExtModeAutoUpdateStatusClock on
BufferReuse on
RTWExpressionDepthLimit 5
SimulationMode "normal"
Solver "ode45"
SolverMode "Auto"
StartTime "0.0"
StopTime "10.0"
MaxOrder 5
MaxStep "auto"
MinStep "auto"
MaxNumMinSteps "-1"
InitialStep "auto"
FixedStep "auto"
RelTol "1e-3"
AbsTol "auto"
OutputOption "RefineOutputTimes"
OutputTimes "[]"
Refine "1"
LoadExternalInput off
ExternalInput "[t, u]"
LoadInitialState off
InitialState "xInitial"
SaveTime on
TimeSaveName "tout"
SaveState off
StateSaveName "xout"
SaveOutput on
OutputSaveName "yout"
SaveFinalState off
FinalStateName "xFinal"
SaveFormat "Array"
Decimation "1"
LimitDataPoints on
MaxDataPoints "1000"
SignalLoggingName "sigsOut"
ConsistencyChecking "none"
ArrayBoundsChecking "none"
AlgebraicLoopMsg "warning"
BlockPriorityViolationMsg "warning"
MinStepSizeMsg "warning"
InheritedTsInSrcMsg "warning"
DiscreteInheritContinuousMsg "warning"
MultiTaskRateTransMsg "error"
SingleTaskRateTransMsg "none"
CheckForMatrixSingularity "none"
IntegerOverflowMsg "warning"
Int32ToFloatConvMsg "warning"
ParameterDowncastMsg "error"
ParameterOverflowMsg "error"
ParameterPrecisionLossMsg "warning"
UnderSpecifiedDataTypeMsg "none"
UnnecessaryDatatypeConvMsg "none"
VectorMatrixConversionMsg "none"
InvalidFcnCallConnMsg "error"
SignalLabelMismatchMsg "none"
UnconnectedInputMsg "warning"
UnconnectedOutputMsg "warning"
UnconnectedLineMsg "warning"
SfunCompatibilityCheckMsg "none"
RTWInlineParameters off
BlockReductionOpt on
BooleanDataType on
ConditionallyExecuteInputs on
ParameterPooling on
OptimizeBlockIOStorage on
ZeroCross on
AssertionControl "UseLocalSettings"
ProdHWDeviceType "Microprocessor"
ProdHWWordLengths "8,16,32,32"
RTWSystemTargetFile "grt.tlc"
RTWTemplateMakefile "grt_default_tmf"
RTWMakeCommand "make_rtw"
RTWGenerateCodeOnly off
RTWRetainRTWFile off
TLCProfiler off
TLCDebug off
TLCCoverage off
TLCAssertion off
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
BlockParameterDefaults {
Block {
BlockType Constant
Value "1"
VectorParams1D on
ShowAdditionalParam off
OutDataTypeMode "Inherit from 'Constant value'"
OutDataType "sfix(16)"
ConRadixGroup "Use specified scaling"
OutScaling "2^0"
}
Block {
BlockType Inport
Port "1"
PortDimensions "-1"
SampleTime "-1"
ShowAdditionalParam off
LatchInput off
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
Interpolate on
}
Block {
BlockType Logic
Operator "AND"
Inputs "2"
ShowAdditionalParam off
AllPortsSameDT on
OutDataTypeMode "Logical (see Advanced Sim. Parameters)"
LogicDataType "uint(8)"
}
Block {
BlockType Outport
Port "1"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType Product
Inputs "2"
Multiplication "Element-wise(.*)"
ShowAdditionalParam off
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
}
Block {
BlockType Sin
SineType "Time based"
Amplitude "1"
Bias "0"
Frequency "1"
Phase "0"
Samples "10"
Offset "0"
SampleTime "-1"
VectorParams1D on
}
Block {
BlockType SubSystem
ShowPortLabels on
Permissions "ReadWrite"
RTWSystemCode "Auto"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType Switch
Criteria "u2 >= Threshold"
Threshold "0"
ShowAdditionalParam off
InputSameDT on
OutDataTypeMode "Inherit via internal rule"
RndMeth "Floor"
SaturateOnIntegerOverflow on
ZeroCross on
}
Block {
BlockType UnitDelay
X0 "0"
SampleTime "1"
RTWStateStorageClass "Auto"
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "pcm_bianma"
Location [2, 74, 774, 539]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Constant
Name "Constant"
Position [120, 172, 150, 188]
}
Block {
BlockType Constant
Name "Constant1"
Position [120, 212, 150, 228]
Value "0"
}
Block {
BlockType Constant
Name "Constant10"
Position [710, 167, 740, 183]
}
Block {
BlockType Constant
Name "Constant11"
Position [710, 222, 740, 238]
Value "0"
}
Block {
BlockType Constant
Name "Constant12"
Position [705, 282, 735, 298]
}
Block {
BlockType Constant
Name "Constant13"
Position [710, 337, 740, 353]
Value "0"
}
Block {
BlockType Constant
Name "Constant14"
Position [710, 397, 740, 413]
}
Block {
BlockType Constant
Name "Constant15"
Position [715, 447, 745, 463]
Value "0"
}
Block {
BlockType Constant
Name "Constant2"
Position [130, 272, 160, 288]
}
Block {
BlockType Constant
Name "Constant3"
Position [125, 327, 155, 343]
Value "0"
}
Block {
BlockType Constant
Name "Constant4"
Position [405, 172, 435, 188]
}
Block {
BlockType Constant
Name "Constant5"
Position [405, 222, 435, 238]
Value "0"
}
Block {
BlockType Constant
Name "Constant6"
Position [410, 297, 440, 313]
}
Block {
BlockType Constant
Name "Constant7"
Position [410, 357, 440, 373]
}
Block {
BlockType Constant
Name "Constant8"
Position [710, 52, 740, 68]
}
Block {
BlockType Constant
Name "Constant9"
Position [705, 107, 735, 123]
Value "0"
}
Block {
BlockType Logic
Name "Logical\nOperator"
Ports [8, 1]
Position [965, 564, 1005, 746]
Inputs "8"
AllPortsSameDT off
}
Block {
BlockType Sin
Name "Sine Wave"
Position [15, 185, 45, 215]
SineType "Time based"
SampleTime "0"
}
Block {
BlockType SubSystem
Name "Subsystem"
Ports [2, 2]
Position [245, 234, 345, 276]
TreatAsAtomicUnit off
System {
Name "Subsystem"
Location [116, 171, 614, 471]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [105, 103, 135, 117]
}
Block {
BlockType Inport
Name "In2"
Position [105, 193, 135, 207]
Port "2"
}
Block {
BlockType Logic
Name "Logical\nOperator"
Ports [1, 1]
Position [170, 184, 200, 216]
Operator "NOT"
AllPortsSameDT off
}
Block {
BlockType Product
Name "Product"
Ports [2, 1]
Position [220, 101, 265, 134]
InputSameDT off
}
Block {
BlockType Product
Name "Product1"
Ports [2, 1]
Position [220, 161, 265, 194]
InputSameDT off
}
Block {
BlockType Outport
Name "Out1"
Position [325, 113, 355, 127]
}
Block {
BlockType Outport
Name "Out2"
Position [325, 173, 355, 187]
Port "2"
}
Line {
SrcBlock "Product1"
SrcPort 1
DstBlock "Out2"
DstPort 1
}
Line {
SrcBlock "Logical\nOperator"
SrcPort 1
Points [5, 0; 0, -15]
DstBlock "Product1"
DstPort 2
}
Line {
SrcBlock "Product"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
Line {
SrcBlock "In1"
SrcPort 1
Points [15, 0]
Branch {
DstBlock "Product"
DstPort 1
}
Branch {
Points [0, 60]
DstBlock "Product1"
DstPort 1
}
}
Line {
Labels [1, 0]
SrcBlock "In2"
SrcPort 1
Points [30, 0]
Branch {
DstBlock "Logical\nOperator"
DstPort 1
}
Branch {
Labels [2, 0]
Points [-25, 0; 0, -75]
DstBlock "Product"
DstPort 2
}
}
Annotation {
Position [205, 198]
}
}
}
Block {
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