;/******************************************************************************
; *
; * Copyright (c) 2003 Windond Electronics Corp.
; * All rights reserved.
; *
; * $Workfile: init.s $
; *
; * $Author: Wschang0 $
; ******************************************************************************/
;/*
; * $History: init.s $
; 
; *****************  Version 2  *****************
; User: Wschang0     Date: 03/08/20   Time: 11:51a
; Updated in $/W90N740/FIRMWARE/WBLv1_1/Src
; Add VSS header
; */


        AREA    Init, CODE, READONLY

; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs

Mode_USR        EQU     0x10
Mode_FIQ        EQU     0x11
Mode_IRQ        EQU     0x12
Mode_SVC        EQU     0x13
Mode_ABT        EQU     0x17
Mode_UNDEF      EQU     0x1B
Mode_SYS        EQU     0x1F ; available on ARM Arch 4 and later

I_Bit           EQU     0x80 ; when I bit is set, IRQ is disabled
F_Bit           EQU     0x40 ; when F bit is set, FIQ is disabled


; --- System memory locations
RAM_Limit       EQU     0x400000          	; For unexpanded W90N740 board

UND_Stack		EQU		RAM_Limit
Abort_Stack		EQU		RAM_Limit-256
IRQ_Stack       EQU     RAM_Limit-512       ; followed by IRQ stack
FIQ_Stack       EQU     RAM_Limit-768       ; followed by IRQ stack
SVC_Stack       EQU     RAM_Limit-1024      ; SVC stack at top of memory
; add FIQ_Stack, ABT_Stack, UNDEF_Stack here if you need them
USR_Stack       EQU     0x3f8000	       ; followed by USR(SYS) stack

ROM_Start       EQU     0x7F000000          ; Base address of ROM after remapping

Clk_Skew		EQU		0xFFF01F00			; W90N740 clock skew control register
EBI_Ctrl		EQU		0xFFF01000			; W90N740 EBI Controle register
SDRAM_config0	EQU		0xFFF01008			; W90N740 SDCONF0

CAHCON			EQU		0xFFF02000			; W90N740 Cache control register

IDREG			EQU		0xFFF00000			; W90N740 CHIP ID

AIC_MDCR		EQU		0xFFF82124			; W90N740 AIC Mask Disable Control Register
AIC_IMR			EQU		0xFFF82114			; W90N740 AIC Mask Disable Control Register
AIC_MECR		EQU		0xFFF82120			; W90N740 AIC Mask Disable Control Register
AIC_SCR7		EQU		0xFFF8201C			; W90N740 AIC Mask Disable Control Register
 
GPIO_AFG	 	EQU		0xFFF83000			;/* configuration Register */
GPIO_DIR	 	EQU		0xFFF83004 			;/* direction Register */
GPIO_DATAOUT 	EQU		0xFFF83008 			;/* GPIO data output Register */
GPIO_DATAIN  	EQU		0xFFF8300C		 	;/* GPIO data input Register */
DEBNCE_CTRL    	EQU		0xFFF83010			;/* debounce control Register */
 
 
COPY_START1			EQU		0x7F003000	; pointer to ROM code
COPY_END1			EQU		0x7F023000	; end of ROM code	//128k program		
COPY_START2			EQU		0x7F001000	; pointer to ROM code
COPY_END2			EQU		0x7F003000	; end of ROM code	//8k downloader


_RAM_STARTADDRESS	EQU		0			; start of RAM 

 
 
	KEEP

	ENTRY
	EXPORT	Reset_Go
Reset_Go

;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

   	LDR		r0, =GPIO_AFG
   	LDR		r1, =0x00000010
	STR		r1, [r0]			
					;//enable uart port ,others is GPIO
    
   	LDR		r0, =GPIO_DIR
   	LDR		r1, =0x0002300d
	STR		r1, [r0]			

   	LDR		r0, =DEBNCE_CTRL
   	LDR		r1, =0
	STR		r1, [r0]		
 					;//disable debug mode
   	LDR		r0, =GPIO_DATAOUT
   	LDR		r1, =0x00022FFD
	STR		r1, [r0]			
;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++


	; Disable Interrupt, This is for safe ...
	LDR	r0, =AIC_MDCR
	LDR	r1, =0x7FFFE
	STR	r1, [r0]
;	MRS	r0, CPSR
;	ORR	r0, r0, #0xC0
;	MSR	CPSR_c, r0

	; Disable cache, This is for safe ...
	MOV		r0, #0x0
	LDR		r1, =CAHCON
	STR		r0, [r1], #4
	MOV		r0, #0x87
	STR		r0, [r1]
11
	LDR		r0, [r1]
	CMP		r0, #0
	BNE		%B11

 	; Check if the system had been initialized
	LDR   r0, =SDRAM_config0
	LDR   r0, [r0]
	LDR	  r1, =0x800
	CMP   r0, r1
	BNE   Reset_Handler

    ; Check version number of W90N740 to set the clock skew
    ; The clock skew of W90N740 version A should be 0x7A
    ; The clock skew of W90N740 version B should be 0x39
    LDR		r0, =IDREG
    LDR		r0, [r0]
    LDR		r1, =0x0F000000
    ANDS	r0,r0,r1
    BEQ		version0
    LDR		r1, =0x01000000
    CMP		r0, r1
    BEQ		version1
    B		unknow_version
version0
	LDR		r0, =0x0FF007A
    B		update_clkskew
version1    
	LDR		r0, =0x0FF0039
    B		update_clkskew
update_clkskew
	LDR		r1, =0xFFF01F00
	STR		r0,[r1]		
unknow_version


; Set mode to SVC, interrupts disabled (just paranoid)
	MRS   r0, cpsr
	BIC   r0, r0, #0x1F
	ORR   r0, r0, #0xD3
	MSR   cpsr_fc, r0

;	Configure the System Manger to remap the flash

; The Memory Bank Control Registers must be set using store multpiles
; Set up a stack in internal sram to preserve the original register contents

	LDR	r2, =remap_temp
	MOV	r1, pc
	LDR r3, =remap_EndSysMapJump
remap_temp
	MOV lr, #0
	CMP	r2, r1
	LDRGE 	lr, =ROM_Start

	SUB	r3, r3, r2
	ADD	r1, r1, r3
	ADD	lr, lr, r1
	
; Load in the target values into the control registers
   	ADRL    r0, remap_SystemInitData
 	LDMIA   r0, {r1-r6}
 	LDR	r0, =EBI_Ctrl
	
; Now run critical jump code
 	STMIA   r0, {r1-r6}
 	MOV	pc, lr
remap_EndSysMapJump

	B	Reset_Handler


; SDRAM is now at address 0x0.
; The exception vectors (in vectors.s) must be copied from ROM to the RAM
; The copying is done later by the C library code inside __main


Reset_Handler

; --- Initialise stack pointer registers
        MSR     CPSR_c, #Mode_UNDEF:OR:I_Bit:OR:F_Bit
        LDR     SP, =UND_Stack

        MSR     CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit 
        LDR     SP, =Abort_Stack

        MSR     CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
        LDR     SP, =IRQ_Stack

        MSR     CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
        LDR     SP, =FIQ_Stack

        MSR     CPSR_c, #Mode_SYS:OR:I_Bit:OR:F_Bit
        LDR     SP, =USR_Stack

        MSR     CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
        LDR     SP, =SVC_Stack

; Set up other stack pointers if necessary
        ; ...

; --- Initialise memory system
        ; ...
; --- Initialise critical IO devices
        ; ...

; --- Initialise interrupt system variables here
        ; ...

; --- Now change to User mode and set up User mode stack.
;        MSR     CPSR_c, #Mode_USR ; No interrupts
;        LDR     SP, =USR_Stack


;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

	LDR		r0,=GPIO_DATAIN
    LDR		r1,[r0]
	BIC		r1,r1,#0xffefffff	
    mov		r0,r1,lsr #20
    cmp		r0,#1
    bne		copy1

    ldr     r0, =COPY_START1	; pointer to ROM code
    ldr     r1, =COPY_END1		; end of ROM code

    b		copy
copy1

    ldr     r0, =COPY_START2	; pointer to ROM code
    ldr     r1, =COPY_END2		; end of ROM code

copy
    ;********************************************************
    ;*	Copy code from ROM to RAM			    *
    ;********************************************************
    ldr     r2, =_RAM_STARTADDRESS	; start of RAM 
0
    cmp     r0, r1
    beq     %F1
    
    ldrb	r3,[r0],#1
    ldrb	r4,[r0],#1
    ldrb	r5,[r0],#1
    ldrb	r6,[r0],#1
    add		r3,r3,r4,lsl #8
    add		r3,r3,r5,lsl #16
    add		r3,r3,r6,lsl #24
    
    str     r3, [r2], #4
    bcc     %B0

1    

	LDR	r0, =AIC_IMR
	LDR	r1, =0x80
	STR	r1, [r0]

	LDR	r0, =AIC_MECR
	LDR	r1, =0x80
	STR	r1, [r0]

	LDR	r0, =AIC_SCR7
	LDR	r1, =0x41
	STR	r1, [r0]


	LDR	PC,=_RAM_STARTADDRESS	;jump to RAM
	B	.						
	

99  B	%99

; --- If no C code, just try to exit by semihosed swi
remap_SystemInitData
	DCD	0x000530C0					; EBICON : not need to change.
	DCD	0xfe000FF0					; ROMCON(Flash) -Unknown type:0xFE000FF0, A29LV800: 0xFE020080, W28J160: 0xFE030080
	DCD	0x000090E3					; SDCONF0(SDRAM) - 8M(2Mx32): 0x000090E3, 4M(1Mx16x2):0x00009062, 16M(4Mx16x2):0x000090E4 			
	DCD	0x01000000					; SDCONF1 - The same as SDCONF0 with proper base address   
	DCD	0x0000014B					; SDTIME0 - not need to change
	DCD	0x00000000					; SDTIME1 - not need to change


	END