module tb ();

reg 			reset, clk;
wire			en, err;
wire [7 : 0]	dat;

reg clken;

ethtest U_ETHTEST( reset, clk, clken, dat, en, clken, dat, en, err );

initial
begin
	reset <= 0;
	#50 reset <= 1;
end

always
begin
	# 10 clk = 1;
	# 10 clk = 0;
end

always @ ( posedge clk, negedge reset )
begin
	if( ! reset )
		clken <= 0;
	else
		clken <= ~ clken;
end

endmodule