library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity tb is
end tb;

architecture tb_arch of tb is
component MII_Proc is
port
(
      MII_ParDat_out : out std_logic_vector(7 downto 0) ;
      MII_ParEN_out : out std_logic ;
      MII_ParClk_out : out std_logic ;					-- use rising_edge to send the data
      MII_ParDat_in : in std_logic_vector(7 downto 0) ;
      MII_ParEN_in : in std_logic ;
      MII_SerDat_in : in std_logic_vector(3 downto 0) ;
      MII_SerEN_in : in std_logic ;
      MII_SerClk_in : out std_logic ;
	  MII_SerERR_in : in std_logic ;
      MII_SerDat_out : out std_logic_vector(3 downto 0) ;
      MII_SerEN_out : out std_logic ;
      MII_SerClk_out : out std_logic ;
	  MII_SerERR_out : out std_logic ;
	  MII_crs : out std_logic ;
	  MII_col : out std_logic ;
	  MII_link : out std_logic ;
	  Serdes_syn : in std_logic ;
	  Opt_LOS : in std_logic ;
      clk_50M : in std_logic ;
	  clk_25M : in std_logic ;
	  rxclken	: in std_logic;
	  clk_12m5 : in std_logic ;
	  rate		: in std_logic_vector( 6 downto 0 );
	  test		: in std_logic;
	  err		: out std_logic;
	  rxpkcnt 	: out std_logic_vector(15 downto 0) ;
	  txpkcnt 	: out std_logic_vector(15 downto 0) ;
	  clr_rxpkcnt : in std_logic;
	  clr_txpkcnt : in std_logic;
	  reset : in std_logic 
);
end component;

signal pardat : std_logic_vector( 7 downto 0 );
signal pardat_out : std_logic_vector( 7 downto 0 );
signal paren_out : std_logic;
signal paren : std_logic;
signal parclk : std_logic;
signal serdat_in : std_logic_vector( 3 downto 0 );
signal seren_in : std_logic;
signal sererr_in : std_logic;
signal serdes_syn : std_logic := '0';
signal opt_los : std_logic;
signal serclk_in : std_logic;
signal serclk_out : std_logic;
signal seren_out : std_logic;
signal serdat_out : std_logic_vector( 3 downto 0 );

signal clk50, clk25, clk12tmp, clk12, reset : std_logic;
signal clk25_1, clk12_1: std_logic;
signal cnt : integer;

signal cnt_in : integer := 0;
signal cnt_out : integer := 0;

signal aclr, discard, rxfifo_ready : std_logic;

signal err : std_logic;
signal ttt : std_logic;
signal dummy : std_logic;
signal dummy_vec : std_logic_vector( 7 downto 0 );

signal crs0, crs1, col0, col1, link0, link1 : std_logic; 
signal wraddr : std_logic_vector( 3 downto 0 );
signal rdaddr : std_logic_vector( 3 downto 0 );

signal cntclr : std_logic;
signal test : std_logic;
signal rate : std_logic_vector( 6 downto 0 );

signal rxclken0 : std_logic;
signal rxclken1 : std_logic;

signal rxpkcnt0	: std_logic_vector( 15 downto 0 );
signal rxpkcnt1	: std_logic_vector( 15 downto 0 );
signal txpkcnt0	: std_logic_vector( 15 downto 0 );
signal txpkcnt1	: std_logic_vector( 15 downto 0 );
begin

test 		<= '0';
cntclr 		<= '0';
rate 		<= conv_std_logic_vector( 20, 7 );

rxclken0 	<= parclk;
rxclken1 	<= parclk;

dummy 		<= '0';
dummy_vec 	<= ( others => '0');

process( seren_in )
begin
	if( rising_edge(seren_in) ) then
		cnt_in <= cnt_in + 1;
	end if;
end process;

process( seren_out )
begin
	if( rising_edge(seren_out) ) then
		cnt_out <= cnt_out + 1;
	end if;
end process;

U_MII_0 : MII_Proc port map
(
      MII_ParDat_out => pardat,
      MII_ParEN_out  => paren,
      MII_ParClk_out => parclk,
      MII_ParDat_in => dummy_vec,
      MII_ParEN_in => dummy,
      MII_SerDat_in => serdat_in,
      MII_SerEN_in => seren_in,
      MII_SerClk_in => open,
	  MII_SerERR_in => sererr_in,
      MII_SerDat_out => open,
      MII_SerEN_out => open,
      MII_SerClk_out => open,
	  MII_SerERR_out => open,
	  MII_crs => crs0,
	  MII_col => col0,
	  MII_link => link0,
	  Serdes_syn => serdes_syn,
	  Opt_LOS => opt_los,
      clk_50M => clk50,
	  clk_25M => clk25,
	  clk_12m5 => clk12,
	  rxclken => rxclken0,
	  rate		=> rate,
	  test		=> test,
	  err		=> open,
	  rxpkcnt 	=> rxpkcnt0,
	  txpkcnt 	=> txpkcnt0,
	  clr_rxpkcnt => cntclr,
	  clr_txpkcnt => cntclr,
	  reset  => reset
);

process( parclk, reset )
begin
	if( rising_edge( parclk ) ) then
		pardat_out <= pardat;
		paren_out	<= paren;
	end if;

	if( reset = '0' ) then
		pardat_out <= pardat;
		paren_out	<= paren;
	end if;
end process;


U_MII_1 : MII_Proc port map
(
      MII_ParDat_out => open,
      MII_ParEN_out  => open,
      MII_ParClk_out => open,
      MII_ParDat_in => pardat_out,
      MII_ParEN_in => paren_out,
      MII_SerDat_in => "0000",
      MII_SerEN_in => dummy,
      MII_SerClk_in => open,
	  MII_SerERR_in => sererr_in,
      MII_SerDat_out => serdat_out,
      MII_SerEN_out => seren_out,
      MII_SerClk_out => serclk_out,
	  MII_SerERR_out => open,
	  MII_crs => crs1,
	  MII_col => col1,
	  MII_link => link1,
	  Serdes_syn => serdes_syn,
	  Opt_LOS => opt_los,
      clk_50M => clk50,
	  clk_25M => clk25_1,
	  clk_12m5 => clk12_1,
	  rxclken => rxclken1,
	  rate		=> rate,
	  test		=> test,
	  err		=> open,
	  rxpkcnt 	=> rxpkcnt1,
	  txpkcnt 	=> txpkcnt1,
	  clr_rxpkcnt => cntclr,
	  clr_txpkcnt => cntclr,
	  reset  => reset
);

process
begin
	reset <= '0';
	wait for 80 ns;
	reset <= '1';
	wait;
end process;

process
begin
	clk25 <= '0';
	wait for 20 ns;
	clk25 <= '1';
	wait for 20 ns;
end process;

process
begin
	clk25_1 <= '0';
	wait for 20 ns;
	clk25_1 <= '1';
	wait for 20 ns;
end process;

process( clk25_1, reset )
begin
	if rising_edge( clk25_1 ) then
		clk12_1 <= not clk12_1;
	end if;

	if reset = '0' then
		clk12_1 <= '0';
	end if;
end process;

process( clk25, reset )
begin
	if rising_edge( clk25 ) then
		clk12 <= clk12tmp;
		clk12tmp <= not clk12tmp;
	end if;

	if reset = '0' then
		clk12tmp <= '0';
	end if;
end process;

process( clk25_1, reset )
	variable dat : std_logic_vector( 3 downto 0 );
begin
	if rising_edge( clk25_1 ) then
		ttt <= seren_out;
		if( seren_out = '0' ) then
			if ( ttt = '1' ) and ( serdat_out /= "0011" ) then
				err <= '1';
			else
				err <= '0';
			end if;
			dat := "0000";
		else
			if dat /= serdat_out then
				err <= '1';
			else
				err <= '0';
			end if;
			dat := dat + '1';
		end if;

	end if;

	if reset = '0' then
		err <= '0';
		dat := "0000";
	end if;
end process;

process( clk25, reset )
	variable dat : std_logic_vector( 3 downto 0 );
	variable len : integer := 20;
	variable ts : std_logic := '0';
begin
	if rising_edge( clk25 ) then
		if( cnt = 49 ) then
			--len := len + 2;
			cnt <= 0;
			seren_in <= '1';
			ts := '0';
			dat := "0000";
			serdat_in <= dat;
		else
			ts := not ts;
			
			if ts = '1' then
				dat := dat + 1;
				serdat_in <= dat;
			else
				dat := dat + 1;
				serdat_in <= dat;
				--serdat_in <= "0000";
			end if;
			cnt <= cnt + 1;
			if( cnt = len ) then
				seren_in <= '0';
			end if;
		end if;

	end if;

	if reset = '0' then
		cnt <= 0;
		seren_in <= '0';
		dat := "0000";
	end if;
end process;
end tb_arch;