?? fw.lst
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268 3 }
269 2 break;
270 2 case SC_CLEAR_FEATURE: // *** Clear Feature
271 2 switch(SETUPDAT[0])
272 2 {
273 3 case FT_DEVICE: // Device
274 3 if(SETUPDAT[2] == 1)
275 3 Rwuen = FALSE; // Disable Remote Wakeup
276 3 else
277 3 EZUSB_STALL_EP0(); // Stall End Point 0
278 3 break;
279 3 case FT_ENDPOINT: // End Point
280 3 if(SETUPDAT[2] == 0)
281 3 {
282 4 if (SETUPDAT[4] == 0x2)
283 4 {
284 5 ResetAndArmEp2();
285 5 TOGCTL = 0x2;
286 5 TOGCTL = 0x22; // reset data toggle
287 5 EP2CS = 0; // Clear stall bit
288 5 }
289 4 else if (SETUPDAT[4] == 0x88)
290 4 {
291 5 TOGCTL = 0x18;
292 5 TOGCTL = 0x38; // reset data toggle
293 5 EP8CS = 0; // Clear stall bit
294 5 }
295 4 else
296 4 EZUSB_STALL_EP0(); // Stall End Point 0
297 4 }
298 3 else
299 3 EZUSB_STALL_EP0(); // Stall End Point 0
300 3 break;
301 3 }
C51 COMPILER V7.50 FW 11/07/2006 14:52:08 PAGE 6
302 2 break;
303 2 case SC_SET_FEATURE: // *** Set Feature
304 2 switch(SETUPDAT[0])
305 2 {
306 3 case FT_DEVICE: // Device
307 3 if(SETUPDAT[2] == 1)
308 3 Rwuen = TRUE; // Enable Remote Wakeup
309 3 else if(SETUPDAT[2] == 2)
310 3 // Set Feature Test Mode. The core handles this request. However, it is
311 3 // necessary for the firmware to complete the handshake phase of the
312 3 // control transfer before the chip will enter test mode. It is also
313 3 // necessary for FX2 to be physically disconnected (D+ and D-)
314 3 // from the host before it will enter test mode.
315 3 break;
316 3 else
317 3 EZUSB_STALL_EP0(); // Stall End Point 0
318 3 break;
319 3 case FT_ENDPOINT: // End Point
320 3 if(SETUPDAT[2] == 0)
321 3 {
322 4 if (SETUPDAT[4] == 0x2)
323 4 EP2CS = bmEPSTALL; // Set stall bit
324 4 else if (SETUPDAT[4] == 0x88)
325 4 EP8CS = bmEPSTALL; // Set stall bit
326 4 else
327 4 EZUSB_STALL_EP0(); // Stall End Point 0
328 4 }
329 3 else
330 3 EZUSB_STALL_EP0(); // Stall End Point 0
331 3 break;
332 3 }
333 2 break;
334 2
335 2 // This is a first attempt at completing a mass storage reset. It is not yet tested.
336 2 case SC_MASS_STORAGE_RESET:
337 2 // Verify that the command is actually a MS reset command sent to the proper interface
338 2 if (SETUPDAT[0] == 0x21 && SETUPDAT[4] == 0) // Our interface number is hard coded (0) in DSCR.A
-51
339 2 {
340 3 // All we really need to do in response to a MSC Reset is restart using
341 3 // a soft reset (jump to 0x00). This will re-initialize the drive and
342 3 // endpoints.
343 3 EZUSB_IRQ_CLEAR();
344 3 INT2CLR = bmSUDAV; // Clear SUDAV IRQ
345 3
346 3 // force a soft reset after the iret.
347 3 EA = 0;
348 3 softReset();
349 3 }
350 2 else
351 2 EZUSB_STALL_EP0(); // Stall End Point 0
352 2 break;
353 2
354 2 default: // *** Invalid Command
355 2 EZUSB_STALL_EP0(); // Stall End Point 0
356 2 }
357 1
358 1 // Acknowledge handshake phase of device request
359 1 // Required for rev C does not effect rev B
360 1 EP0CS |= bmHSNAK;
361 1 }
362
C51 COMPILER V7.50 FW 11/07/2006 14:52:08 PAGE 7
363 // Wake-up interrupt handler
364 void resume_isr(void) interrupt WKUP_VECT
365 {
366 1 EZUSB_CLEAR_RSMIRQ();
367 1 }
368
369 STRINGDSCR xdata * EZUSB_GetStringDscr(BYTE StrIdx)
370 {
371 1 extern BYTE code StringDscr0;
372 1 extern BYTE code StringDscr1;
373 1 extern BYTE code StringDscr2;
374 1 extern BYTE code StringDscr3;
375 1
376 1 switch (StrIdx)
377 1 {
378 2 case 0:
379 2 return((STRINGDSCR xdata *)&StringDscr0);
380 2 case 1:
381 2 return((STRINGDSCR xdata *)&StringDscr1);
382 2 case 2:
383 2 return((STRINGDSCR xdata *)&StringDscr2);
384 2 case 3:
385 2 return((STRINGDSCR xdata *)&StringDscr3);
386 2 default:
387 2 return(0);
388 2 }
389 1 }
C51 COMPILER V7.50 FW 11/07/2006 14:52:08 PAGE 8
ASSEMBLY LISTING OF GENERATED OBJECT CODE
; FUNCTION main (BEGIN)
; SOURCE LINE # 66
; SOURCE LINE # 67
; SOURCE LINE # 71
0000 E4 CLR A
0001 F500 E MOV MaxPIO,A
; SOURCE LINE # 72
0003 C200 R CLR Sleep
; SOURCE LINE # 73
0005 C200 R CLR Rwuen
; SOURCE LINE # 74
0007 C200 R CLR Selfpwr
; SOURCE LINE # 79
0009 120000 E LCALL abortGPIF
; SOURCE LINE # 81
000C 120000 E LCALL TD_Init
; SOURCE LINE # 87
000F 7E00 E MOV R6,#HIGH halfKBuffer
0011 7F00 E MOV R7,#LOW halfKBuffer
0013 7C00 E MOV R4,#HIGH DeviceDscr
0015 7D00 E MOV R5,#LOW DeviceDscr
0017 7A00 E MOV R2,#HIGH DscrEndOffset
0019 7B00 E MOV R3,#LOW DscrEndOffset
001B 120000 E LCALL _mymemmovexx
; SOURCE LINE # 95
001E AF00 R MOV R7,intrfcSubClass
0020 7400 E MOV A,#LOW halfKBuffer
0022 2400 E ADD A,#LOW IntrfcSubClassFullSpeedOffset
0024 F582 MOV DPL,A
0026 7400 E MOV A,#HIGH halfKBuffer
0028 3400 E ADDC A,#HIGH IntrfcSubClassFullSpeedOffset
002A F583 MOV DPH,A
002C EF MOV A,R7
002D F0 MOVX @DPTR,A
002E 7400 E MOV A,#LOW halfKBuffer
0030 2400 E ADD A,#LOW IntrfcSubClassHighSpeedOffset
0032 F582 MOV DPL,A
0034 7400 E MOV A,#HIGH halfKBuffer
0036 3400 E ADDC A,#HIGH IntrfcSubClassHighSpeedOffset
0038 F583 MOV DPH,A
003A EF MOV A,R7
003B F0 MOVX @DPTR,A
; SOURCE LINE # 98
;---- Variable 'i' assigned to Register 'R7' ----
003C E4 CLR A
003D FF MOV R7,A
003E ?C0001:
; SOURCE LINE # 99
003E 7400 E MOV A,#LOW localSerialNumber
0040 2F ADD A,R7
0041 F8 MOV R0,A
0042 E6 MOV A,@R0
0043 FE MOV R6,A
0044 EF MOV A,R7
0045 2400 E ADD A,#LOW SerialNumberOffset
0047 FD MOV R5,A
0048 E4 CLR A
0049 3400 E ADDC A,#HIGH SerialNumberOffset
004B FC MOV R4,A
C51 COMPILER V7.50 FW 11/07/2006 14:52:08 PAGE 9
004C 7400 E MOV A,#LOW halfKBuffer
004E 2D ADD A,R5
004F F582 MOV DPL,A
0051 7400 E MOV A,#HIGH halfKBuffer
0053 3C ADDC A,R4
0054 F583 MOV DPH,A
0056 EE MOV A,R6
0057 F0 MOVX @DPTR,A
0058 0F INC R7
0059 BF18E2 CJNE R7,#018H,?C0001
005C ?C0002:
; SOURCE LINE # 101
005C D2E8 SETB EUSB
; SOURCE LINE # 102
005E 43D820 ORL EICON,#020H
; SOURCE LINE # 104
0061 90E668 MOV DPTR,#0E668H
0064 E0 MOVX A,@DPTR
0065 4408 ORL A,#08H
0067 F0 MOVX @DPTR,A
; SOURCE LINE # 106
0068 90E65C MOV DPTR,#0E65CH
006B E0 MOVX A,@DPTR
006C 4439 ORL A,#039H
006E F0 MOVX @DPTR,A
; SOURCE LINE # 107
006F D2AF SETB EA
; SOURCE LINE # 114
0071 90E680 MOV DPTR,#0E680H
0074 E0 MOVX A,@DPTR
0075 20E105 JB ACC.1,?C0004
; SOURCE LINE # 115
; SOURCE LINE # 116
0078 D200 E SETB ?EZUSB_Discon?BIT
007A 120000 E LCALL EZUSB_Discon
; SOURCE LINE # 117
007D ?C0004:
; SOURCE LINE # 124
007D E580 MOV A,IOA
007F 30E609 JNB ACC.6,?C0005
; SOURCE LINE # 125
; SOURCE LINE # 126
0082 90E680 MOV DPTR,#0E680H
0085 E0 MOVX A,@DPTR
0086 54F7 ANL A,#0F7H
0088 F0 MOVX @DPTR,A
; SOURCE LINE # 127
0089 8003 SJMP ?C0006
008B ?C0005:
; SOURCE LINE # 129
; SOURCE LINE # 130
008B 120000 R LCALL DisconAndWaitForVbus
; SOURCE LINE # 131
008E ?C0006:
; SOURCE LINE # 139
008E 538EF8 ANL CKCON,#0F8H
; SOURCE LINE # 145
0091 90E6A0 MOV DPTR,#0E6A0H
0094 E0 MOVX A,@DPTR
0095 4480 ORL A,#080H
0097 F0 MOVX @DPTR,A
0098 ?C0007:
C51 COMPILER V7.50 FW 11/07/2006 14:52:08 PAGE 10
; SOURCE LINE # 148
; SOURCE LINE # 149
; SOURCE LINE # 154
0098 E580 MOV A,IOA
009A 20E603 JB ACC.6,?C0009
; SOURCE LINE # 155
009D 120000 R LCALL DisconAndWaitForVbus
00A0 ?C0009:
; SOURCE LINE # 158
00A0 120000 E LCALL TD_Poll
; SOURCE LINE # 159
00A3 80F3 SJMP ?C0007
; FUNCTION main (END)
; FUNCTION DisconAndWaitForVbus (BEGIN)
; SOURCE LINE # 166
; SOURCE LINE # 167
; SOURCE LINE # 168
0000 90E680 MOV DPTR,#0E680H
0003 E0 MOVX A,@DPTR
0004 4408 ORL A,#08H
0006 F0 MOVX @DPTR,A
0007 ?C0011:
; SOURCE LINE # 169
0007 E580 MOV A,IOA
0009 30E6FB JNB ACC.6,?C0011
000C ?C0012:
; SOURCE LINE # 170
000C 90E680 MOV DPTR,#0E680H
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