?? fx2regs.lst
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A51 MACRO ASSEMBLER FX2REGS 11/07/2006 14:50:05 PAGE 1
MACRO ASSEMBLER A51 V7.10
NO OBJECT MODULE REQUESTED
ASSEMBLER INVOKED BY: C:\Keil\C51\BIN\A51.EXE C:\Cypress\USB\Target\Inc\fx2regs.inc SET(SMALL) DEBUG PRINT(.\fx2regs.lst
) OBJECT(.\fx2regs.obj) EP
LOC OBJ LINE SOURCE
1 ;-----------------------------------------------------------------------------
2 ; File: FX2regs.inc
3 ; Contents: EZ-USB FX2 register declarations and bit mask definitions.
4 ; This file is the equivalent of fx2regs.h but for assembley
code
5 ; Do not modify one without modifying the other.
6 ;
7 ; Copyright (c) 2000 Cypress Semiconductor, All rights reserved
8 ;-----------------------------------------------------------------------------
9
E400 10 GPIF_WAVE_DATA XDATA 0xE400 ;
E480 11 RES_WAVEDATA_END XDATA 0xE480 ;
12
13 ; General Configuration
14
E600 15 CPUCS XDATA 0xE600 ; Control & Status
E601 16 IFCONFIG XDATA 0xE601 ; Interface Configuration
E602 17 PINFLAGSAB XDATA 0xE602 ; FIFO FLAGA and FLAGB Assignments
E603 18 PINFLAGSCD XDATA 0xE603 ; FIFO FLAGC and FLAGD Assignments
E604 19 FIFORESET XDATA 0xE604 ; Restore FIFOS to default state
E605 20 BREAKPT XDATA 0xE605 ; Breakpoint
E606 21 BPADDRH XDATA 0xE606 ; Breakpoint Address H
E607 22 BPADDRL XDATA 0xE607 ; Breakpoint Address L
E608 23 UART230 XDATA 0xE608 ; 230 Kbaud clock for T0,T1,T2
E609 24 FIFOPINPOLAR XDATA 0xE609 ; FIFO polarities
E60A 25 REVID XDATA 0xE60A ; Chip Revision
E60B 26 REVCTL XDATA 0xE60B ; Chip Revision Control
27
28 ; Endpoint Configuration
29
E610 30 EP1OUTCFG XDATA 0xE610 ; Endpoint 1-OUT Configuration
E611 31 EP1INCFG XDATA 0xE611 ; Endpoint 1-IN Configuration
E612 32 EP2CFG XDATA 0xE612 ; Endpoint 2 Configuration
E613 33 EP4CFG XDATA 0xE613 ; Endpoint 4 Configuration
E614 34 EP6CFG XDATA 0xE614 ; Endpoint 6 Configuration
E615 35 EP8CFG XDATA 0xE615 ; Endpoint 8 Configuration
E618 36 EP2FIFOCFG XDATA 0xE618 ; Endpoint 2 FIFO configuration
E619 37 EP4FIFOCFG XDATA 0xE619 ; Endpoint 4 FIFO configuration
E61A 38 EP6FIFOCFG XDATA 0xE61A ; Endpoint 6 FIFO configuration
E61B 39 EP8FIFOCFG XDATA 0xE61B ; Endpoint 8 FIFO configuration
E620 40 EP2AUTOINLENH XDATA 0xE620 ; Endpoint 2 Packet Length H (IN only)
E621 41 EP2AUTOINLENL XDATA 0xE621 ; Endpoint 2 Packet Length L (IN only)
E622 42 EP4AUTOINLENH XDATA 0xE622 ; Endpoint 4 Packet Length H (IN only)
E623 43 EP4AUTOINLENL XDATA 0xE623 ; Endpoint 4 Packet Length L (IN only)
E624 44 EP6AUTOINLENH XDATA 0xE624 ; Endpoint 6 Packet Length H (IN only)
E625 45 EP6AUTOINLENL XDATA 0xE625 ; Endpoint 6 Packet Length L (IN only)
E626 46 EP8AUTOINLENH XDATA 0xE626 ; Endpoint 8 Packet Length H (IN only)
E627 47 EP8AUTOINLENL XDATA 0xE627 ; Endpoint 8 Packet Length L (IN only)
E630 48 EP2FIFOPFH XDATA 0xE630 ; EP2 Programmable Flag trigger H
E631 49 EP2FIFOPFL XDATA 0xE631 ; EP2 Programmable Flag trigger L
E632 50 EP4FIFOPFH XDATA 0xE632 ; EP4 Programmable Flag trigger H
E633 51 EP4FIFOPFL XDATA 0xE633 ; EP4 Programmable Flag trigger L
E634 52 EP6FIFOPFH XDATA 0xE634 ; EP6 Programmable Flag trigger H
E635 53 EP6FIFOPFL XDATA 0xE635 ; EP6 Programmable Flag trigger L
E636 54 EP8FIFOPFH XDATA 0xE636 ; EP8 Programmable Flag trigger H
E637 55 EP8FIFOPFL XDATA 0xE637 ; EP8 Programmable Flag trigger L
E640 56 EP2ISOINPKTS XDATA 0xE640 ; EP2 (if ISO) IN Packets per frame (1-3)
A51 MACRO ASSEMBLER FX2REGS 11/07/2006 14:50:05 PAGE 2
E641 57 EP4ISOINPKTS XDATA 0xE641 ; EP4 (if ISO) IN Packets per frame (1-3)
E642 58 EP6ISOINPKTS XDATA 0xE642 ; EP6 (if ISO) IN Packets per frame (1-3)
E643 59 EP8ISOINPKTS XDATA 0xE643 ; EP8 (if ISO) IN Packets per frame (1-3)
E648 60 INPKTEND XDATA 0xE648 ; Force IN Packet End
E649 61 OUTPKTEND XDATA 0xE649 ; Force OUT Packet End
62
63 ; Interrupts
64
E650 65 EP2FIFOIE XDATA 0xE650 ; Endpoint 2 Flag Interrupt Enable
E651 66 EP2FIFOIRQ XDATA 0xE651 ; Endpoint 2 Flag Interrupt Request
E652 67 EP4FIFOIE XDATA 0xE652 ; Endpoint 4 Flag Interrupt Enable
E653 68 EP4FIFOIRQ XDATA 0xE653 ; Endpoint 4 Flag Interrupt Request
E654 69 EP6FIFOIE XDATA 0xE654 ; Endpoint 6 Flag Interrupt Enable
E655 70 EP6FIFOIRQ XDATA 0xE655 ; Endpoint 6 Flag Interrupt Request
E656 71 EP8FIFOIE XDATA 0xE656 ; Endpoint 8 Flag Interrupt Enable
E657 72 EP8FIFOIRQ XDATA 0xE657 ; Endpoint 8 Flag Interrupt Request
E658 73 IBNIE XDATA 0xE658 ; IN-BULK-NAK Interrupt Enable
E659 74 IBNIRQ XDATA 0xE659 ; IN-BULK-NAK interrupt Request
E65A 75 NAKIE XDATA 0xE65A ; Endpoint Ping NAK interrupt Enable
E65B 76 NAKIRQ XDATA 0xE65B ; Endpoint Ping NAK interrupt Request
E65C 77 USBIE XDATA 0xE65C ; USB Int Enables
E65D 78 USBIRQ XDATA 0xE65D ; USB Interrupt Requests
E65E 79 EPIE XDATA 0xE65E ; Endpoint Interrupt Enables
E65F 80 EPIRQ XDATA 0xE65F ; Endpoint Interrupt Requests
E660 81 GPIFIE XDATA 0xE660 ; GPIF Interrupt Enable
E661 82 GPIFIRQ XDATA 0xE661 ; GPIF Interrupt Request
E662 83 USBERRIE XDATA 0xE662 ; USB Error Interrupt Enables
E663 84 USBERRIRQ XDATA 0xE663 ; USB Error Interrupt Requests
E664 85 ERRCNTLIM XDATA 0xE664 ; USB Error counter and limit
E665 86 CLRERRCNT XDATA 0xE665 ; Clear Error Counter EC[3..0]
E666 87 INT2IVEC XDATA 0xE666 ; Interupt 2 (USB) Autovector
E667 88 INT4IVEC XDATA 0xE667 ; Interupt 4 (FIFOS & GPIF) Autovector
E668 89 INTSETUP XDATA 0xE668 ; Interrupt 2&4 Setup
90
91 ; Input/Output
92
E670 93 PORTACFG XDATA 0xE670 ; I/O PORTA Alternate Configuration
E671 94 PORTCCFG XDATA 0xE671 ; I/O PORTC Alternate Configuration
E672 95 PORTECFG XDATA 0xE672 ; I/O PORTE Alternate Configuration
E678 96 I2CS XDATA 0xE678 ; Control & Status
E679 97 I2DAT XDATA 0xE679 ; Data
E67A 98 I2CTL XDATA 0xE67A ; I2C Control
E67B 99 EXTAUTODAT1 XDATA 0xE67B ; Autoptr1 MOVX access
E67C 100 EXTAUTODAT2 XDATA 0xE67C ; Autoptr2 MOVX access
101
102 ; USB Control
103
E680 104 USBCS XDATA 0xE680 ; USB Control & Status
E681 105 SUSPEND XDATA 0xE681 ; Put chip into suspend
E682 106 WAKEUPCS XDATA 0xE682 ; Wakeup source and polarity
E683 107 TOGCTL XDATA 0xE683 ; Toggle Control
E684 108 USBFRAMEH XDATA 0xE684 ; USB Frame count H
E685 109 USBFRAMEL XDATA 0xE685 ; USB Frame count L
E686 110 MICROFRAME XDATA 0xE686 ; Microframe count, 0-7
E687 111 FNADDR XDATA 0xE687 ; USB Function address
112
113 ; Endpoints
114
E68A 115 EP0BCH XDATA 0xE68A ; Endpoint 0 Byte Count H
E68B 116 EP0BCL XDATA 0xE68B ; Endpoint 0 Byte Count L
E68D 117 EP1OUTBC XDATA 0xE68D ; Endpoint 1 OUT Byte Count
E68F 118 EP1INBC XDATA 0xE68F ; Endpoint 1 IN Byte Count
E690 119 EP2BCH XDATA 0xE690 ; Endpoint 2 Byte Count H
E691 120 EP2BCL XDATA 0xE691 ; Endpoint 2 Byte Count L
E694 121 EP4BCH XDATA 0xE694 ; Endpoint 4 Byte Count H
E695 122 EP4BCL XDATA 0xE695 ; Endpoint 4 Byte Count L
A51 MACRO ASSEMBLER FX2REGS 11/07/2006 14:50:05 PAGE 3
E698 123 EP6BCH XDATA 0xE698 ; Endpoint 6 Byte Count H
E699 124 EP6BCL XDATA 0xE699 ; Endpoint 6 Byte Count L
E69C 125 EP8BCH XDATA 0xE69C ; Endpoint 8 Byte Count H
E69D 126 EP8BCL XDATA 0xE69D ; Endpoint 8 Byte Count L
E6A0 127 EP0CS XDATA 0xE6A0 ; Endpoint Control and Status
E6A1 128 EP1OUTCS XDATA 0xE6A1 ; Endpoint 1 OUT Control and Status
E6A2 129 EP1INCS XDATA 0xE6A2 ; Endpoint 1 IN Control and Status
E6A3 130 EP2CS XDATA 0xE6A3 ; Endpoint 2 Control and Status
E6A4 131 EP4CS XDATA 0xE6A4 ; Endpoint 4 Control and Status
E6A5 132 EP6CS XDATA 0xE6A5 ; Endpoint 6 Control and Status
E6A6 133 EP8CS XDATA 0xE6A6 ; Endpoint 8 Control and Status
E6A7 134 EP2FIFOFLGS XDATA 0xE6A7 ; Endpoint 2 Flags
E6A8 135 EP4FIFOFLGS XDATA 0xE6A8 ; Endpoint 4 Flags
E6A9 136 EP6FIFOFLGS XDATA 0xE6A9 ; Endpoint 6 Flags
E6AA 137 EP8FIFOFLGS XDATA 0xE6AA ; Endpoint 8 Flags
E6AB 138 EP2FIFOBCH XDATA 0xE6AB ; EP2 FIFO total byte count H
E6AC 139 EP2FIFOBCL XDATA 0xE6AC ; EP2 FIFO total byte count L
E6AD 140 EP4FIFOBCH XDATA 0xE6AD ; EP4 FIFO total byte count H
E6AE 141 EP4FIFOBCL XDATA 0xE6AE ; EP4 FIFO total byte count L
E6AF 142 EP6FIFOBCH XDATA 0xE6AF ; EP6 FIFO total byte count H
E6B0 143 EP6FIFOBCL XDATA 0xE6B0 ; EP6 FIFO total byte count L
E6B1 144 EP8FIFOBCH XDATA 0xE6B1 ; EP8 FIFO total byte count H
E6B2 145 EP8FIFOBCL XDATA 0xE6B2 ; EP8 FIFO total byte count L
E6B3 146 SUDPTRH XDATA 0xE6B3 ; Setup Data Pointer high address byte
E6B4 147 SUDPTRL XDATA 0xE6B4 ; Setup Data Pointer low address byte
E6B5 148 SUDPTRCTL XDATA 0xE6B5 ; Setup Data Pointer Auto Mode
E6B8 149 SETUPDAT XDATA 0xE6B8 ; 8 bytes of SETUP data
150
151 ; GPIF
152
E6C0 153 GPIFWFSELECT XDATA 0xE6C0 ; Waveform Selector
E6C1 154 GPIFIDLECS XDATA 0xE6C1 ; GPIF Done, GPIF IDLE drive mode
E6C2 155 GPIFIDLECTL XDATA 0xE6C2 ; Inactive Bus, CTL states
E6C3 156 GPIFCTLCFG XDATA 0xE6C3 ; CTL OUT pin drive
E6C4 157 GPIFADRH XDATA 0xE6C4 ; GPIF Address H
E6C5 158 GPIFADRL XDATA 0xE6C5 ; GPIF Address L
159
160
E6CE 161 GPIFTCB3 XDATA 0xE6CE ; GPIF Transaction Count Byte 3
E6CF 162 GPIFTCB2 XDATA 0xE6CF ; GPIF Transaction Count Byte 2
E6D0 163 GPIFTCB1 XDATA 0xE6D0 ; GPIF Transaction Count Byte 1
E6D1 164 GPIFTCB0 XDATA 0xE6D1 ; GPIF Transaction Count Byte 0
165
166
E6D0 167 EP2GPIFTCH EQU GPIFTCB1 ; these are here for backwards compatibility
E6D1 168 EP2GPIFTCL EQU GPIFTCB0 ; before REVE silicon (ie. REVB and REVD)
E6D0 169 EP4GPIFTCH EQU GPIFTCB1 ; these are here for backwards compatibility
E6D1 170 EP4GPIFTCL EQU GPIFTCB0 ; before REVE silicon (ie. REVB and REVD)
E6D0 171 EP6GPIFTCH EQU GPIFTCB1 ; these are here for backwards compatibility
E6D1 172 EP6GPIFTCL EQU GPIFTCB0 ; before REVE silicon (ie. REVB and REVD)
E6D0 173 EP8GPIFTCH EQU GPIFTCB1 ; these are here for backwards compatibility
E6D1 174 EP8GPIFTCL EQU GPIFTCB0 ; before REVE silicon (ie. REVB and REVD)
175
176
177 ; EP2GPIFTCH XDATA 0xE6D0 ; EP2 GPIF Transaction Count High
178 ; EP2GPIFTCL XDATA 0xE6D1 ; EP2 GPIF Transaction Count Low
E6D2 179 EP2GPIFFLGSEL XDATA 0xE6D2 ; EP2 GPIF Flag select
E6D3 180 EP2GPIFPFSTOP XDATA 0xE6D3 ; Stop GPIF EP2 transaction on prog. flag
E6D4 181 EP2GPIFTRIG XDATA 0xE6D4 ; EP2 FIFO Trigger
182 ; EP4GPIFTCH XDATA 0xE6D8 ; EP4 GPIF Transaction Count High
183 ; EP4GPIFTCL XDATA 0xE6D9 ; EP4 GPIF Transactionr Count Low
E6DA 184 EP4GPIFFLGSEL XDATA 0xE6DA ; EP4 GPIF Flag select
E6DB 185 EP4GPIFPFSTOP XDATA 0xE6DB ; Stop GPIF EP4 transaction on prog. flag
E6DC 186 EP4GPIFTRIG XDATA 0xE6DC ; EP4 FIFO Trigger
187 ; EP6GPIFTCH XDATA 0xE6E0 ; EP6 GPIF Transaction Count High
188 ; EP6GPIFTCL XDATA 0xE6E1 ; EP6 GPIF Transaction Count Low
A51 MACRO ASSEMBLER FX2REGS 11/07/2006 14:50:05 PAGE 4
E6E2 189 EP6GPIFFLGSEL XDATA 0xE6E2 ; EP6 GPIF Flag select
E6E3 190 EP6GPIFPFSTOP XDATA 0xE6E3 ; Stop GPIF EP6 transaction on prog. flag
E6E4 191 EP6GPIFTRIG XDATA 0xE6E4 ; EP6 FIFO Trigger
192 ; EP8GPIFTCH XDATA 0xE6E8 ; EP8 GPIF Transaction Count High
193 ; EP8GPIFTCL XDATA 0xE6E9 ; EP8GPIF Transaction Count Low
E6EA 194 EP8GPIFFLGSEL XDATA 0xE6EA ; EP8 GPIF Flag select
E6EB 195 EP8GPIFPFSTOP XDATA 0xE6EB ; Stop GPIF EP8 transaction on prog. flag
E6EC 196 EP8GPIFTRIG XDATA 0xE6EC ; EP8 FIFO Trigger
E6F0 197 XGPIFSGLDATH XDATA 0xE6F0 ; GPIF Data H (16-bit mode only)
E6F1 198 XGPIFSGLDATLX XDATA 0xE6F1 ; Read/Write GPIF Data L & trigger transac
E6F2 199 XGPIFSGLDATLNOX XDATA 0xE6F2 ; Read GPIF Data L, no transac trigger
E6F3 200 GPIFREADYCFG XDATA 0xE6F3 ; Internal RDY,Sync/Async, RDY5CFG
E6F4 201 GPIFREADYSTAT XDATA 0xE6F4 ; RDY pin states
E6F5 202 GPIFABORT XDATA 0xE6F5 ; Abort GPIF cycles
203
204 ; UDMA
205
E6C6 206 FLOWSTATE XDATA 0xE6C6 ; Defines GPIF flow state
E6C7 207 FLOWLOGIC XDATA 0xE6C7 ; Defines flow/hold decision criteria
E6C8 208 FLOWEQ0CTL XDATA 0xE6C8 ; CTL states during active flow state
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