/* 
 * This GEL file (init.gel) is loaded on the command line 
 * of Code Composer. It provides example code on how to 
 * reset the C6x DSP and initialize the External Memory Interface.
 *
 * You may have to edit settings in emif_init() to your own 
 * specifications as the example is applicable to the C6x EVM.
 *
 */



/*
 * The StartUp() function is called every time you start
 * Code Composer.  You can customize this function to
 * initialize wait states in the EMIF or to perform 
 * other initialization.
 */
StartUp()
{
    /* uncomment the following line to initialize the
       EMIF registers on the C6x when Code Composer starts up */

	/* emif_init();  */
}



/*
 * Menuitem creates a selection available beneath the GEL
 * menu selection in Code Composer Studio.
 */
menuitem "Resets";

hotmenu Reset_and_EMIF_Setup()
{
	GEL_Reset();
	emif_init();
}

hotmenu Reset_EMIFset_and_ClearBreakPts()
{
	GEL_Reset();
	emif_init();
	GEL_BreakPtReset();
}




/*********************************************/


emif_init()
{
/*---------------------------------------------------------------------------*/
/* EMIF REGISTER VALUES FROM SPRU269B                                        */
/*---------------------------------------------------------------------------*/

	#define EMIF_GCTL       0x01800000
	#define EMIF_CE1        0x01800004
	#define EMIF_CE0        0x01800008
	#define EMIF_CE2        0x01800010
	#define EMIF_CE3        0x01800014
	#define EMIF_SDRAMCTL   0x01800018
	#define EMIF_SDRAMREF   0x0180001c



/***********************************************************
 * Edit values below to conform to your specifications
 * The following assumes the EVM6x memory configuration
 ***********************************************************/

        /* OK for 133, 160 MHK CPU clock rate */
        *(int *)EMIF_GCTL = 0x3060;

        /* CE1 */
        *(int *)EMIF_CE1 = 0x0b300a21;

        /* CE0 SBSRAM */
        *(int *)EMIF_CE0 = 0x40;

        /* CE2 and CE3 SDRAM */
        *(int *)EMIF_CE2 = 0x30;
        *(int *)EMIF_CE3 = 0x0b300a21;

        /* 133 MHz, use 0x7227000 for 160 MHz */
        *(int *)EMIF_SDRAMCTL = 0x7116000;

        /* 133 MHz, use 0x4e1 for 160 MHz */
        *(int *)EMIF_SDRAMREF = 0x410;
}