/**********************************************************************************/
/*                                                                                */
/*    Copyright (C) 2006 Oki Electric Industry Co., LTD.                          */
/*                                                                                */
/*    System Name    :  ML675050                                                  */
/*    Module Name    :  ML675050 header file                                      */
/*    File   Name    :  ML675050.h                                                */
/*    Revision       :  1.00                                                      */
/*    Date           :  2006/02/10                                                */
/*                                                                                */
/**********************************************************************************/
#ifndef ML675050_H
#define ML675050_H

#ifdef __cplusplus
extern "C" {
#endif



/*****************************************************/
/*    Interrupt Control Register                     */
/*****************************************************/
#define ICR_BASE        0x78000000              /* base address of Interrupt Control Register */
#define IRQ             (ICR_BASE+0x00)         /* IRQ register */
#define IRQS            (ICR_BASE+0x04)         /* Software IRQ register */
#define FIQ             (ICR_BASE+0x08)         /* FIQ register */
#define FIQRAW          (ICR_BASE+0x0C)         /* FIQ RAW register */
#define FIQEN           (ICR_BASE+0x10)         /* FIQ enable register */
#define IRN             (ICR_BASE+0x14)         /* IRQ number register */
#define CIL             (ICR_BASE+0x18)         /* Current IRQ level register */
#define ILC0            (ICR_BASE+0x20)         /* IRQ level control register 0 */
#define ILC1            (ICR_BASE+0x24)         /* IRQ level control register 1 */
#define CILCL           (ICR_BASE+0x28)         /* Current IRQ level clear register */
#define CILE            (ICR_BASE+0x2C)         /* Current IRQ level encode register */

/* bit field of IRQ register */
#define IRQ_IRQ0                0x00000001      /* IR0 */
#define IRQ_IRQ1                0x00000002      /* IR1 */
#define IRQ_IRQ2                0x00000004      /* IR2 */
#define IRQ_IRQ3                0x00000008      /* IR3 */
#define IRQ_IRQ4                0x00000010      /* IR4 */
#define IRQ_IRQ5                0x00000020      /* IR5 */
#define IRQ_IRQ6                0x00000040      /* IR6 */
#define IRQ_IRQ7                0x00000080      /* IR7 */
#define IRQ_IRQ8                0x00000100      /* IR8 */
#define IRQ_IRQ9                0x00000200      /* IR9 */
#define IRQ_IRQ10               0x00000400      /* IR10 */
#define IRQ_IRQ11               0x00000800      /* IR11 */
#define IRQ_IRQ12               0x00001000      /* IR12 */
#define IRQ_IRQ13               0x00002000      /* IR13 */
#define IRQ_IRQ14               0x00004000      /* IR14 */
#define IRQ_IRQ15               0x00008000      /* IR15 */

/* bit field of IRQS register */
#define IRQS_IRQS               0x00000002

/* bit field of FIQ register */
#define FIQ_FIQ                 0x00000001

/* bit field of FIQRAW register */
#define FIQRAW_FIQRAW           0x00000001      /* FIQ interrupt signal status */

/* bit field of FIQEN register */
#define FIQEN_FIQEN             0x00000001      /* Enable FIQ interrupr request */

/* bit field of IRN register */
#define IRN_IRN                 0x0000003F      /* Interrupt source number with the highest priority  */

/* bit field of CIL register */
#define CIL_CIL1                0x00000002      /* Level 1 interrupt */
#define CIL_CIL2                0x00000004      /* Level 2 interrupt */
#define CIL_CIL3                0x00000008      /* Level 3 interrupt */
#define CIL_CIL4                0x00000010      /* Level 4 interrupt */
#define CIL_CIL5                0x00000020      /* Level 5 interrupt */
#define CIL_CIL6                0x00000040      /* Level 6 interrupt */
#define CIL_CIL7                0x00000080      /* Level 7 interrupt */

/* bit field of ILC0 register */
#define ILC0_ILR0               0x00000007      /* IR0 */
#define ILC0_ILR1               0x00000070      /* IR1,IR2,IR3 */
#define ILC0_ILR4               0x00070000      /* IR4,5 */
#define ILC0_ILR6               0x07000000      /* IR6,7 */

/* bit field of ILC1 register */
#define ILC1_ILR8               0x00000007      /* IR8 */
#define ILC1_ILR9               0x00000070      /* IR9 */
#define ILC1_ILR10              0x00000700      /* IR10 */
#define ILC1_ILR11              0x00007000      /* IR11 */
#define ILC1_ILR12              0x00070000      /* IR12 */
#define ILC1_ILR13              0x00700000      /* IR13 */
#define ILC1_ILR14              0x07000000      /* IR14 */
#define ILC1_ILR15              0x70000000      /* IR15 */

/* bit field of CILE register */
#define CILE_CILE               0x00000007


/*****************************************************/
/*    External Memory Control Regsiter               */
/*****************************************************/
#define EMCR_BASE       0x78100000              /* base address of External Memory Control Regsiter */
#define BWC             (EMCR_BASE+0x00)        /* Bus width control register */
#define ROMAC           (EMCR_BASE+0x04)        /* ROM access control register */
#define RAMAC           (EMCR_BASE+0x08)        /* SRAM access control register */
#define IOAC            (EMCR_BASE+0x0C)        /* External I/O access control register */

/* bit field of BWC register */
#define BWC_ROMBW               0x0000000C      /* ROM area bus width */
#define BWC_RAMBW               0x00000030      /* RAM area bus width */
#define BWC_IOBW                0x000000C0      /* IO area bus width */

/* bit field of ROMAC register */
#define ROMAC_ROMTYPE           0x00000007      /* ROM access timing */
#define ROMAC_ROMBRST           0x00000010      /* Pagemode ROM */

/* bit field of RAMAC register */
#define RAMAC_RAMTYPE           0x00000007      /* RAM access timing */
#define RAMAC_RAMBRST           0x00000010      /* Pagemode RAM */

/* bit field of IOAC register */
#define IOAC_IOTYPE             0x00000007      /* IO access timing */


/*****************************************************/
/*    DRAM Control Register                          */
/*****************************************************/
#define DCR_BASE        0x78180000              /* base address of DRAM Control Register */
#define DBWC            (DCR_BASE+0x00)         /* DRAM bus width control register */
#define DRMC            (DCR_BASE+0x04)         /* DRAM control register */
#define DRPC            (DCR_BASE+0x08)         /* DRAM characteristic parameter control register */
#define SDMD            (DCR_BASE+0x0C)         /* DRAM mode register */
#define DCMD            (DCR_BASE+0x10)         /* DRAM command register */
#define RFSH            (DCR_BASE+0x14)         /* External input refresh cycle control register */
#define PDWC            (DCR_BASE+0x18)         /* SDRAM power-down mode control regsiter */
#define RFGC            (DCR_BASE+0x1C)         /* Self refresh cycle conrol register */

/* bit field of DBWC register */
#define DBWC_BWDRAM             0x00000003      /* SDRAM bus width */

/* bit field of DRMC register */
#define DRMC_AMUX               0x00000003      /* Address multiplex */
#define DRMC_ARCH               0x00000004      /* DRAM type */
#define DRMC_PRELAT             0x00000010      /* Pre-charge latancy at SDRAM reading */
#define DRMC_PDWN               0x00000040      /* Enable automatic SDRAM power-down mode */
#define DRMC_RFRSH              0x00000080      /* Control dtstribution CBR refresh */

/* bit field of DRPC register */
#define DRPC_DRAMSPEC           0x0000000F      /* DRAM access timing */

/* bit field of SDMD register */
#define SDMD_LTMODE             0x00000001      /* SDRAM CAS latency */
#define SDMD_MODEWR             0x00000080      /* Mode setting */

/* bit field of DCMD register */
#define DCMD_DRCMD              0x00000007      /* Issues SDRAM command */

/* bit field of RFSH register */
#define RFSH_RCCON              0x00000001      /* SDRAM refresh cycle multiplier */

/* bit field of PDWC register */
#define PDWC_PDCNT              0x0000000F      /* Count idle state  */

/* bit field of RFGC register */
#define RFGC_RFSEL              0x00001FFF      /* Control SDRAM refresh cycle */


/*****************************************************/
/*    Cache Control Register                         */
/*****************************************************/
#define CCR_BASE        0x78200004              /* base address of Cache Control Register */
#define CON             (CCR_BASE+0x00)         /* Cache lock control register  */
#define CACHE           (CCR_BASE+0x04)         /* Cacheable register  */
#define FLUSH           (CCR_BASE+0x18)         /* FLUSH register */

/* bit field of CON register */
#define CON_LCK                 0x06000000      /* Select way to lock */
#define CON_F                   0x08000000      /* Set cache memory as load mode  */
#define CON_BNK                 0x30000000      /* Select way to load */

/* bit field of CACHE register */
#define CACHE_C10               0x00000004      /* Enable bank 10 */
#define CACHE_C24               0x00000100      /* Enable bank 24 */
#define CACHE_C25               0x00000200      /* Enable bank 25 */
#define CACHE_C26               0x00000400      /* Enable bank 26 */
#define CACHE_C27               0x00000800      /* Enable bank 27 */
#define CACHE_C28               0x00001000      /* Enable bank 28 */
#define CACHE_C29               0x00002000      /* Enable bank 29 */
#define CACHE_C0                0x00010000      /* Enable bank 0 */


/*****************************************************/
/*    USB2.0FS Host/USB2.0LS Host Control Register   */
/*****************************************************/
#define UHC_BASE        0x7BC00000              /* base address of USB2.0FS Host/USB2.0LS Host Control Register */
#define USBConfig       (UHC_BASE+0x00)         /* USB configuration register */
#define DMACtl          (UHC_BASE+0x04)         /* DMA control register */
#define RstPDownCtl     (UHC_BASE+0x08)         /* Reset power down control register */
#define HostCtl         (UHC_BASE+0x20)         /* Host Control register */
#define SttTrnsCnt      (UHC_BASE+0x24)         /* Status, RD/WR FIFO transfer length register */
#define PktDataTrnsReq  (UHC_BASE+0x28)         /* Packet data transfer request register */
#define RamAdr          (UHC_BASE+0x30)         /* Internal RAM address setting register */
#define FifoAcc         (UHC_BASE+0x40)         /* FIFO access register */
#define USBPortMon      (UHC_BASE+0xA0)         /* USB Port monitor register */
#define USBPortCtl      (UHC_BASE+0xB0)         /* USB Port control register */
#define HcRevision      (UHC_BASE+0x100)        /* HcRevision register */
#define HcControl       (UHC_BASE+0x104)        /* HcControl register */
#define HcCommandStatus (UHC_BASE+0x108)        /* HcCommandStatus register */
#define HcInterruptStatus (UHC_BASE+0x10C)        /* HcInterruptStatus register */
#define HcInterruptEnable (UHC_BASE+0x110)        /* HcInterruptEnable register */
#define HcInterruptDisable (UHC_BASE+0x114)        /* HcInterruptDisable register */
#define HcHCCA          (UHC_BASE+0x118)        /* HcHCCA register */
#define HcPeriodCurrentED (UHC_BASE+0x11C)        /* HcPeriodCurrentED register */
#define HcControlHeadED (UHC_BASE+0x120)        /* HcControlHeadED register */
#define HcControlCurrentED (UHC_BASE+0x124)        /* HcControlCurrentED register */
#define HcBulkHeadED    (UHC_BASE+0x128)        /* HcBulkHeadED register */
#define HcBulkCurrentED (UHC_BASE+0x12C)        /* HcBulkCurrentED register */
#define HcDoneHead      (UHC_BASE+0x130)        /* HcDoneHead register */
#define HcFmInterval    (UHC_BASE+0x134)        /* HcFmInterval register */
#define HcFmRemaining   (UHC_BASE+0x138)        /* HcFmRemaining register */
#define HcFmNumber      (UHC_BASE+0x13C)        /* HcFmNumber register */
#define HcPeriodicStart (UHC_BASE+0x140)        /* HcPeriodicStart register */
#define HcLSThreshold   (UHC_BASE+0x144)        /* HcLSThreshold register */
#define HcRhDescriptorA (UHC_BASE+0x148)        /* HcRhDescriptorA register */
#define HcRhDescriptorB (UHC_BASE+0x14C)        /* HcRhDescriptorB register */