#ifndef MXC_SETUP_MXC91331_H#define MXC_SETUP_MXC91331_H/* * * File: mxc_setup_mxc91331.h * *      Platform specific code for MXC91331 platform. *      This code is derived from eCos files hal_platform_setup.h *///==========================================================================//####ECOSGPLCOPYRIGHTBEGIN####// -------------------------------------------// This file is part of eCos, the Embedded Configurable Operating System.// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.//// eCos is free software; you can redistribute it and/or modify it under// the terms of the GNU General Public License as published by the Free// Software Foundation; either version 2 or (at your option) any later version.//// eCos is distributed in the hope that it will be useful, but WITHOUT ANY// WARRANTY; without even the implied warranty of MERCHANTABILITY or// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License// for more details.//// You should have received a copy of the GNU General Public License along// with eCos; if not, write to the Free Software Foundation, Inc.,// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.//// As a special exception, if other files instantiate templates or use macros// or inline functions from this file, or you compile this file and link it// with other works to produce a work based on this file, this file does not// by itself cause the resulting work to be covered by the GNU General Public// License. However the source code for this file must still be made available// in accordance with section (3) of the GNU General Public License.//// This exception does not invalidate any other reasons why a work based on// this file might be covered by the GNU General Public License.//// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.// at http://sources.redhat.com/ecos/ecos-license/// -------------------------------------------//####ECOSGPLCOPYRIGHTEND####//========================================================================*/#ifdef __ASSEMBLER__#define REG8_VAL(a)          (a)#define REG16_VAL(a)         (a)#define REG32_VAL(a)         (a)#define REG8_PTR(a)          (a)#define REG16_PTR(a)         (a)#define REG32_PTR(a)         (a)#else /* __ASSEMBLER__ */#define REG8_VAL(a)          ((unsigned char)(a))#define REG16_VAL(a)         ((unsigned short)(a))#define REG32_VAL(a)         ((unsigned int)(a))#define REG8_PTR(a)          ((volatile unsigned char *)(a))#define REG16_PTR(a)         ((volatile unsigned short *)(a))#define REG32_PTR(a)         ((volatile unsigned int *)(a))#define readb(a)             (*(volatile unsigned char *)(a))#define readw(a)             (*(volatile unsigned short *)(a))#define readl(a)             (*(volatile unsigned int *)(a))#define writeb(v,a)          (*(volatile unsigned char *)(a) = (v))#define writew(v,a)          (*(volatile unsigned short *)(a) = (v))#define writel(v,a)          (*(volatile unsigned int *)(a) = (v))#endif /* __ASSEMBLER__ *//* * Default Memory Layout Definitions */#define         L2CC_BASE_ADDR          0x30000000/* * AIPS 1 */#define         AIPS1_BASE_ADDR         0x43F00000#define         AIPS1_CTRL_BASE_ADDR    AIPS1_BASE_ADDR#define         MAX_BASE_ADDR           0x43F04000#define         EVTMON_BASE_ADDR        0x43F08000#define         CLKCTL_BASE_ADDR        0x43F0C000  #define         ETB_SLOT4_BASE_ADDR     0x43F10000#define         ETB_SLOT5_BASE_ADDR     0x43F14000#define         ECT_CTIO_BASE_ADDR      0x43F18000#define         I2C_BASE_ADDR           0x43F80000#define         MU_BASE_ADDR            0x43F84000#define         WDOG2_BASE_ADDR         0x43F88000#define         UART1_BASE_ADDR         0x43F90000#define         UART2_BASE_ADDR         0x43F94000#define         OWIRE_BASE_ADDR         0x43F9C000#define         SSI1_BASE_ADDR          0x43FA0000#define         CSPI1_BASE_ADDR         0x43FA4000#define         KPP_BASE_ADDR           0x43FA8000/* * SPBA */#define         SPBA_BASE_ADDR          0x50000000#define         SIM2_BASE_ADDR          0x50000000#define         MMC_SDHC1_BASE_ADDR     0x50004000#define         MMC_SDHC2_BASE_ADDR     0x50008000#define         UART3_BASE_ADDR         0x5000C000#define         CSPI2_BASE_ADDR         0x50010000#define         SSI2_BASE_ADDR          0x50014000#define         SIM1_BASE_ADDR          0x50018000#define         IIM_BASE_ADDR           0x5001C000#define         USBOTG_BASE_ADDR        0x50020000#define         HAC_BASE_ADDR           0x50024000#define         UART4_BASE_ADDR         0x50028000#define         GPIO2_BASE_ADDR         0x5002C000#define         IOMUXC_BASE_ADDR        0x50030000#define         GEMK_BASE_ADDR          0x50034000#define         SDMA_CTI_BASE_ADDR      0x50038000#define         SPBA_CTRL_BASE_ADDR     0x5003C000/* * AIPS 2 */#define         AIPS2_BASE_ADDR         0x53F00000#define         AIPS2_CTRL_BASE_ADDR    AIPS2_BASE_ADDR#define         CRM_MCU_BASE_ADDR       0x53F80000#define         ECT_MCU_CTI_BASE_ADDR   0x53F84000#define         EDIO_BASE_ADDR          0x53F88000#define         FIRI_BASE_ADDR          0x53F8C000#define         GPT_BASE_ADDR           0x53F90000#define         EPIT1_BASE_ADDR         0x53F94000#define         EPIT2_BASE_ADDR         0x53F98000#define         SCC_BASE                0x53FAC000#define         RNG_BASE_ADDR           0x53FB0000#define         RTR_BASE_ADDR           0x53FB4000#define         IPU_CTRL_BASE_ADDR      0x53FC0000#define         AUDMUX_BASE             0x53FC4000#define         MPEG4_ENC_BASE          0x53FC8000#define         GPIO1_BASE_ADDR         0x53FCC000#define         SDMA_BASE_ADDR          0x53FD4000#define         RTC_BASE_ADDR           0x53FD8000#define         WDOG1_BASE_ADDR         0x53FDC000#define         PWM_BASE_ADDR           0x53FE0000#define         RTIC_BASE_ADDR          0x53FEC000/* * ROMPATCH and AVIC */#define         ROMPATCH_BASE_ADDR      0x60000000#define         AVIC_BASE_ADDR          0x68000000/* * NAND, SDRAM, WEIM, M3IF, EMI controllers */#define         EXT_MEM_CTRL_BASE       0xB8000000#define         NFC_BASE                EXT_MEM_CTRL_BASE#define         ESDCTL_BASE             0xB8001000#define         WEIM_BASE_ADDR          0xB8002000#define         WEIM_CTRL_CS0           WEIM_BASE_ADDR#define         WEIM_CTRL_CS1           (WEIM_BASE_ADDR + 0x10)#define         WEIM_CTRL_CS2           (WEIM_BASE_ADDR + 0x20)#define         WEIM_CTRL_CS3           (WEIM_BASE_ADDR + 0x30)#define         WEIM_CTRL_CS4           (WEIM_BASE_ADDR + 0x40)#define         M3IF_BASE               0xB8003000#define         PCMCIA_CTL_BASE         0xB8004000/* * Memory regions and CS */#define         IPU_MEM_BASE_ADDR       0x70000000#define         CSD0_BASE_ADDR          0x80000000#define         CSD1_BASE_ADDR          0x90000000#define         CS0_BASE_ADDR           0xA0000000#define         CS1_BASE_ADDR           0xA8000000#define         CS2_BASE_ADDR           0xB0000000#define         CS3_BASE_ADDR           0xB2000000#define         CS4_BASE_ADDR           0xB4000000#define         CS4_BASE_PSRAM          0xB5000000#define         CS5_BASE_ADDR           0xB6000000#define         PCMCIA_MEM_BASE_ADDR    0xC0000000#define         INTERNAL_ROM_VA         0xF0000000// SDRAM#define         RAM_BANK0_BASE        SDRAM_BASE_ADDR/* * IRQ Controller Register Definitions. */#define         AVIC_NIMASK                 REG32_PTR(AVIC_BASE_ADDR + (0x04))#define         AVIC_INTTYPEH               REG32_PTR(AVIC_BASE_ADDR + (0x18))#define         AVIC_INTTYPEL               REG32_PTR(AVIC_BASE_ADDR + (0x1C))/* L210 */#define         L2CC_BASE_ADDR              0x30000000#define         L2_CACHE_LINE_SIZE          32#define         L2_CACHE_CTL_REG            0x100#define         L2_CACHE_AUX_CTL_REG        0x104#define         L2_CACHE_SYNC_REG           0x730#define         L2_CACHE_INV_LINE_REG       0x770#define         L2_CACHE_INV_WAY_REG        0x77C#define         L2_CACHE_CLEAN_LINE_REG     0x7B0#define         L2_CACHE_CLEAN_INV_LINE_REG 0x7F0/* SPBA */#define         SPBA_IOMUX                  0x30#define         SPBA_GPIO_SDMA              0x2C/* CCM */#define         CLKCTL_MCR                      0x00#define         CLKCTL_PDR0                     0x04#define         CLKCTL_PDR1                     0x08#define         CLKCTL_RCSR                     0x0C#define         CLKCTL_MPCTL                    0x10#define         CLKCTL_UPCTL                    0x14#define         CLKCTL_COSR                     0x18#define         PLL_REF_CLK                     26000000/* WEIM - CS0 */#define         CSCRU                           0x00#define         CSCRL                           0x04#define         CSCRA                           0x08/* ESDCTL */#define         ESDCTL_ESDCTL0                  0x00#define         ESDCTL_ESDCFG0                  0x04#define         ESDCTL_ESDCTL1                  0x08#define         ESDCTL_ESDCFG1                  0x0C#define         ESDCTL_ESDMISC                  0x10/* * UART Control Register 0 Bit Fields. */#define         EUartUCR1_ADEN      (1 << 15)   // Auto detect interrupt#define         EUartUCR1_ADBR      (1 << 14)   // Auto detect baud rate#define         EUartUCR1_TRDYEN    (1 << 13)   // Transmitter ready interrupt enable#define         EUartUCR1_IDEN      (1 << 12)   // Idle condition interrupt#define         EUartUCR1_RRDYEN    (1 << 9)    // Recv ready interrupt enable#define         EUartUCR1_RDMAEN    (1 << 8)    // Recv ready DMA enable#define         EUartUCR1_IREN      (1 << 7)    // Infrared interface enable#define         EUartUCR1_TXMPTYEN  (1 << 6)    // Transimitter empty interrupt enable#define         EUartUCR1_RTSDEN    (1 << 5)    // RTS delta interrupt enable#define         EUartUCR1_SNDBRK    (1 << 4)    // Send break#define         EUartUCR1_TDMAEN    (1 << 3)    // Transmitter ready DMA enable#define         EUartUCR1_DOZE      (1 << 1)    // Doze#define         EUartUCR1_UARTEN    (1 << 0)    // UART enabled#define         EUartUCR2_ESCI      (1 << 15)   // Escape seq interrupt enable#define         EUartUCR2_IRTS      (1 << 14)   // Ignore RTS pin#define         EUartUCR2_CTSC      (1 << 13)   // CTS pin control#define         EUartUCR2_CTS       (1 << 12)   // Clear to send#define         EUartUCR2_ESCEN     (1 << 11)   // Escape enable#define         EUartUCR2_PREN      (1 << 8)    // Parity enable#define         EUartUCR2_PROE      (1 << 7)    // Parity odd/even#define         EUartUCR2_STPB      (1 << 6)    // Stop#define         EUartUCR2_WS        (1 << 5)    // Word size#define         EUartUCR2_RTSEN     (1 << 4)    // Request to send interrupt enable#define         EUartUCR2_ATEN      (1 << 3)    // Aging timer enable#define         EUartUCR2_TXEN      (1 << 2)    // Transmitter enabled#define         EUartUCR2_RXEN      (1 << 1)    // Receiver enabled#define         EUartUCR2_SRST_     (1 << 0)    // SW reset#define         EUartUCR3_PARERREN  (1 << 12)   // Parity enable#define         EUartUCR3_FRAERREN  (1 << 11)   // Frame error interrupt enable#define         EUartUCR3_ADNIMP    (1 << 7)    // Autobaud detection not improved#define         EUartUCR3_RXDSEN    (1 << 6)    // Receive status interrupt enable#define         EUartUCR3_AIRINTEN  (1 << 5)    // Async IR wake interrupt enable#define         EUartUCR3_AWAKEN    (1 << 4)    // Async wake interrupt enable#define         EUartUCR3_RXDMUXSEL (1 << 2)    // RXD muxed input selected#define         EUartUCR3_INVT      (1 << 1)    // Inverted Infrared transmission#define         EUartUCR3_ACIEN     (1 << 0)    // Autobaud counter interrupt enable#define         EUartUCR4_CTSTL_32  (32 << 10)  // CTS trigger level (32 chars)#define         EUartUCR4_INVR      (1 << 9)    // Inverted infrared reception#define         EUartUCR4_ENIRI     (1 << 8)    // Serial infrared interrupt enable#define         EUartUCR4_WKEN      (1 << 7)    // Wake interrupt enable#define         EUartUCR4_IRSC      (1 << 5)    // IR special case#define         EUartUCR4_LPBYP     (1 << 4)    // Low power bypass#define         EUartUCR4_TCEN      (1 << 3)    // Transmit complete interrupt enable#define         EUartUCR4_BKEN      (1 << 2)    // Break condition interrupt enable#define         EUartUCR4_OREN      (1 << 1)    // Receiver overrun interrupt enable#define         EUartUCR4_DREN      (1 << 0)    // Recv data ready interrupt enable#define         EUartUFCR_RXTL_SHF  0           // Receiver trigger level shift#define         EUartUFCR_RFDIV_1   (5 << 7)    // Reference freq divider (div 1)#define         EUartUFCR_RFDIV_2   (4 << 7)    // Reference freq divider (div 2)#define         EUartUFCR_RFDIV_3   (3 << 7)            // Reference freq divider (div 3)#define         EUartUFCR_RFDIV_4   (2 << 7)            // Reference freq divider (div 4)#define         EUartUFCR_RFDIV_5   (1 << 7)            // Reference freq divider (div 5)#define         EUartUFCR_RFDIV_6   (0 << 7)            // Reference freq divider (div 6)#define         EUartUFCR_RFDIV_7   (6 << 7)            // Reference freq divider (div 7)#define         EUartUFCR_TXTL_SHF  10          // Transmitter trigger level shift#define         EUartUSR1_PARITYERR (1 << 15)   // Parity error interrupt flag#define         EUartUSR1_RTSS      (1 << 14)   // RTS pin status#define         EUartUSR1_TRDY      (1 << 13)   // Transmitter ready interrupt/dma flag#define         EUartUSR1_RTSD      (1 << 12)   // RTS delta#define         EUartUSR1_ESCF      (1 << 11)   // Escape seq interrupt flag#define         EUartUSR1_FRAMERR   (1 << 10)   // Frame error interrupt flag#define         EUartUSR1_RRDY      (1 << 9)    // Receiver ready interrupt/dma flag#define         EUartUSR1_AGTIM     (1 << 8)    // Aging timeout interrupt status#define         EUartUSR1_RXDS      (1 << 6)    // Receiver idle interrupt flag#define         EUartUSR1_AIRINT    (1 << 5)    // Async IR wake interrupt flag#define         EUartUSR1_AWAKE     (1 << 4)    // Aysnc wake interrupt flag#define         EUartUSR2_ADET      (1 << 15)   // Auto baud rate detect complete#define         EUartUSR2_TXFE      (1 << 14)   // Transmit buffer FIFO empty#define         EUartUSR2_IDLE      (1 << 12)   // Idle condition#define         EUartUSR2_ACST      (1 << 11)   // Autobaud counter stopped#define         EUartUSR2_IRINT     (1 << 8)    // Serial infrared interrupt flag#define         EUartUSR2_WAKE      (1 << 7)    // Wake#define         EUartUSR2_RTSF      (1 << 4)    // RTS edge interrupt flag#define         EUartUSR2_TXDC      (1 << 3)    // Transmitter complete