?? mxc_setup_mx31.h
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/* * Step 6: M3IF/WEIM/ESDCTL setup */ /* M3IF setup */ /* Configure M3IF registers */ ldr r1, =M3IF_BASE /* * M3IF Control Register (M3IFCTL) * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 * ------------ * 0x00000040 */ ldr r0, =0x00000040 str r0, [r1] /* M3IF control reg */ /* WEIM setup */ /* CS0 setup */ #ifdef FLASH_BURST_MODE_ENABLE /* * Sync mode (AHB Clk = 133MHz ; BCLK = 44.3MHz): */ /* Flash reset command */ ldr r0, =CS0_BASE_ADDR ldr r1, =0xF0F0 strh r1, [r0] /* 1st command */ ldr r2, =0xAAA add r2, r2, r0 ldr r1, =0xAAAA strh r1, [r2] /* 2nd command */ ldr r2, =0x554 add r2, r2, r0 ldr r1, =0x5555 strh r1, [r2] /* 3rd command */ ldr r2, =0xAAA add r2, r2, r0 ldr r1, =0xD0D0 strh r1, [r2] /* Write flash config register */ ldr r1, =0x56CA strh r1, [r2] /* Flash reset command */ ldr r1, =0xF0F0 strh r1, [r0] /* WEIM setup */ ldr r0, =WEIM_BASE_ADDR ldr r1, =0x23524E80 str r1, [r0, #CSCRU] ldr r1, =0x10000D03 str r1, [r0, #CSCRL] ldr r1, =0x00720900 str r1, [r0, #CSCRA] #else /* Async flash mode */ ldr r0, =WEIM_CTRL_CS0 ldr r1, =0x11414C80 str r1, [r0, #CSCRU] ldr r1, =0x30000D03 str r1, [r0, #CSCRL] ldr r1, =0x00310800 str r1, [r0, #CSCRA] #endif /* CPLD on CS4 setup */ ldr r0, =WEIM_CTRL_CS4 ldr r1, =0x0000D843 str r1, [r0, #CSCRU] ldr r1, =0x22252521 str r1, [r0, #CSCRL] ldr r1, =0x22220A00 str r1, [r0, #CSCRA] init_sdram: /* Get here only when not boot out of SDRAM */ /* * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits * in SW_PAD_CTL registers */ // SDCLK ldr r1, =(IOMUXC_BASE_ADDR + 0x26C) ldr r0, [r1] bic r0, r0, #(1 << 12) str r0, [r1] ldr r1, =(IIM_BASE_ADDR + 0x30) ldrb r0, [r1] orr r0, r0, #(1 << 1) strb r0, [r1] // CAS ldr r1, =(IOMUXC_BASE_ADDR + 0x270) ldr r0, [r1] bic r0, r0, #(1 << 22) str r0, [r1] // RAS ldr r1, =(IOMUXC_BASE_ADDR + 0x274) ldr r0, [r1] bic r0, r0, #(1 << 2) str r0, [r1] // CS2 (CSD0) ldr r1, =(IOMUXC_BASE_ADDR + 0x27C) ldr r0, [r1] bic r0, r0, #(1 << 22) str r0, [r1] // DQM3 ldr r1, =(IOMUXC_BASE_ADDR + 0x284) ldr r0, [r1] bic r0, r0, #(1 << 22) str r0, [r1] ldr r1, =(IIM_BASE_ADDR + 0x34) ldrb r0, [r1] orr r0, r0, #(1 << 1) strb r0, [r1] // DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) ldr r1, =(IOMUXC_BASE_ADDR + 0x288) ldr r2, =22 // (0x2E0 - 0x288) / 4 = 22 pad_loop: ldr r0, [r1] bic r0, r0, #(1 << 22) bic r0, r0, #(1 << 12) bic r0, r0, #(1 << 2) str r0, [r1] add r1, r1, #4 subs r2, r2, #0x1 bne pad_loop /* Assuming DDR memory first */ ldr r3, =0x82226c80 /* 32 bit memory */ init_ddr_sdram /* Testing if it is truly DDR */ ldr r1, =SDRAM_COMPARE_CONST1 ldr r0, =SDRAM_BASE_ADDR str r1, [r0] ldr r2, =SDRAM_COMPARE_CONST2 str r2, [r0, #0x4] ldr r2, [r0] cmp r1, r2 beq HWInitialise_skip_SDRAM_setup ldr r3, =0x82214C80 /* 16 bit memory */ init_ddr_sdram /* Testing if it is truly DDR */ ldr r1, =SDRAM_COMPARE_CONST1 ldr r0, =SDRAM_BASE_ADDR str r1, [r0] ldr r2, =SDRAM_COMPARE_CONST2 str r2, [r0, #0x4] ldr r2, [r0] cmp r1, r2 beq HWInitialise_skip_SDRAM_setup /* Reach here ONLY when SDR */ ldr r3, =0x82126180 /* 32 bit memory */ init_sdr_sdram /* Still test to make sure SDR */ ldr r1, =SDRAM_COMPARE_CONST1 ldr r0, =SDRAM_BASE_ADDR str r1, [r0] ldr r2, =SDRAM_COMPARE_CONST2 str r2, [r0, #0x4] ldr r2, [r0] cmp r1, r2 beq HWInitialise_skip_SDRAM_setup ldr r3, =0x82116180 /* 16 bit memory */ init_sdr_sdram /* Still test to make sure SDR */ ldr r1, =SDRAM_COMPARE_CONST1 ldr r0, =SDRAM_BASE_ADDR str r1, [r0] ldr r2, =SDRAM_COMPARE_CONST2 str r2, [r0, #0x4] ldr r2, [r0] cmp r1, r2 beq HWInitialise_skip_SDRAM_setup /* Reach hear means memory setup problem. Try to * increase the HCLK divider */ ldr r0, =CRM_MCU_BASE_ADDR ldr r1, [r0, #CLKCTL_PDR0] and r2, r1, #0x38 cmp r2, #0x38 beq loop_forever add r1, r1, #0x8 str r1, [r0, #CLKCTL_PDR0] b init_sdram loop_forever: b loop_forever /* shouldn't get here */ HWInitialise_skip_SDRAM_setup: /* * End of Step 7: M3IF/WEIM/ESDCTL setupa */ HWInitialise_skip_SDRAM_copy: skip_dsp_reset: /* End of DSP reset */ NAND_ClockSetup: .endm .macro init_ddr_sdram ldr r0, =ESDCTL_BASE ldr r2, =SDRAM_BASE_ADDR ldr r1, =0x006AC73A str r1, [r0, #0x4] ldr r1, =0x2 // reset str r1, [r0, #0x10] ldr r1, =0x4 // DDR str r1, [r0, #0x10] // Hold for more than 200ns ldr r1, =0x10000 1: subs r1, r1, #0x1 bne 1b ldr r1, =0x92100000 str r1, [r0] ldr r1, =0x12344321 ldr r12, =0x80000F00 str r1, [r12] ldr r1, =0xA2100000 str r1, [r0] ldr r1, =0x12344321 str r1, [r2] str r1, [r2] ldr r1, =0xB2100000 str r1, [r0] ldr r1, =0xDA strb r1, [r2, #0x33] ldr r1, =0xFF ldr r12, =0x81000000 strb r1, [r12] str r3, [r0] ldr r1, =0xDEADBEEF str r1, [r2] ldr r1, =0x0000000C str r1, [r0, #0x10] .endm // SDR SDRAM setup /* r3 = value for ESDCTL0 */ .macro init_sdr_sdram /* * Jason: We don't know compile SDRAM setup code because we don't have the * current ipl is already very large and we don't have room for the code */ #if 0 ldr r0, =ESDCTL_BASE ldr r2, =SDRAM_BASE_ADDR ldr r1, =0x0075E73A str r1, [r0, #0x4] ldr r1, =0x2 // reset str r1, [r0, #0x10] ldr r1, =0x0 // sdr str r1, [r0, #0x10] // Hold for more than 200ns ldr r1, =0x10000 1: subs r1, r1, #0x1 bne 1b ldr r1, =0x92126080 str r1, [r0] ldr r1, =0x0 ldr r12, =0x80000400 str r1, [r12] ldr r1, =0xA2126080 str r1, [r0] ldr r1, =0x0 str r1, [r2] str r1, [r2] ldr r1, =0xB2126080 str r1, [r0] ldr r1, =0x0 strb r1, [r2, #0x37] ldr r12, =0x81000000 str r1, [r12] str r3, [r0] ldr r1, =0x0 str r1, [r2] #endif .endm#endif /* defined(__ASSEMBLER__) */#endif /* MXC_SETUP_MX31_H_ */?? 快捷鍵說明
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