/* *  misc/source/bootloader/nandboot/mxc_nb_uart.h * *  Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA *//*! * @file mxc_nb_uart.h *  * @brief This file contains the UART register information.  * *  * @ingroup NANDboot */#ifndef MXC_NB_UART_H#define MXC_NB_UART_H#include "mxc_nb.h"/*! Maximum length of the string */#define MAX_STRLEN              200 //150/* Definitions form  redboot\cvs\src\packages\hal\arm\mxc91131\var\current\include\hal_mxc91131.h */#ifdef MXC91131enum plls {    MCU_PLL,    USB_PLL,    DSP_PLL,};enum main_clocks {    CPU_CLK,    AHB_CLK,    IPG_CLK,    NFC_CLK,    USB_CLK,};enum peri_clocks {    UART1_BAUD,    UART2_BAUD,    UART3_BAUD,    SSI1_BAUD,    SSI2_BAUD,    CSI_BAUD,};enum iomux_pins {    /* IOMUX for AP side */    AD1_RXD = 0,    AD1_TXC,    AD1_TXD,    AD1_TXFS,    AD2_RXD,    AD2_TXC,    AD2_TXD,    AD2_TXFS,    AD3_RXC,    AD3_RXD,    AD3_RXFS,    AD3_TXC,    AD3_TXD,    AD3_TXFS,    ALE,    BMOD0,    BMOD1,    BMOD2,    BSY_B,    CE_B,    CLE,    CSI_D0,    CSI_D1,    CSI_D2,    CSI_D3,    CSI_D4,    CSI_D5,    CSI_D6,    CSI_D7,    CSI_D8,    CSI_D9,    CSI_HSYNC,    CSI_PIXCLK,    CSI_VSYNC,    ED_INT0,    ED_INT1,    ED_INT2,    ED_INT3,    ED_INT4,    ED_INT5,    ED_INT6,    ED_INT7,    U1_TXD,    U1_RXD,    IPU_LD17_D0_VSYNC,    IPU_D3_CLK_CONTR,    IPU_D3_DRDY_SP,    IPU_SER_RS,    IPU_D2_CS,    U1_RTS_B,    IPU_REV_D1_CS,    IPU_SD_D,    IPU_SD_CLK,    U1_CTS_B,    U2_TXD,    U2_RXD,    U2_CTS_B,    U2_RTS_B,    SPI1_SS1,    GP_AP_C0,    GP_AP_C1,    GP_AP_C10,    GP_AP_C11,    ICAP1,    ICK_AP,    OC1,    OC2,    OC3,    ICAP2,    GP_AP_C2,    CSI_MCLK,    IPU_D3_VSYNC_BE0,    IPU_D3_HSYNC_BE1,    IPU_LD16_D0_CS,    IPU_D3_CONTR_PAR_RS,    GP_AP_C3,    IPU_D3_SPL_RD,    IPU_D3_CLS_WR,    GP_AP_C4,    GP_AP_C5,    GP_AP_C6,    GP_AP_C7,    GP_AP_C8,    GP_AP_C9,    I2CLK,    I2DAT,    IPU_LD0,    IPU_LD1,    IPU_LD10,    IPU_LD11,    IPU_LD12,    IPU_LD13,    IPU_LD14,    IPU_LD15,    IPU_LD2,    IPU_LD3,    IPU_LD4,    IPU_LD5,    IPU_LD6,    IPU_LD7,    IPU_LD8,    IPU_LD9,    KPCOL0,    KPCOL1,    KPCOL2,    KPCOL3,    KPCOL4,    KPCOL5,    KPCOL6,    KPCOL7,    KPROW0,    KPROW1,    KPROW2,    KPROW3,    KPROW4,    KPROW5,    KPROW6,    KPROW7,    OWDAT,    RE_B,    SPI1_CLK,    SPI1_MISO,    SPI1_MOSI,    SPI1_SS0,    WE_B,    WP_B,    /* IOMUX shared between AP and BP */    USB_DAT_VP,    USB_SE0_VM,    UH2_OVR,    UH2_PWR,    UH1_TXOE_B,    UH1_SPEED,    UH1_SUSPEND,    UH1_TXDP,    UH1_TXDM,    USB_TXOE_B,    UH1_RXD,    UH1_RXDP,    SD1_CMD,    SD1_CLK,    SD1_MMC_PU_CTRL,    UH1_RXDM,    SD2_CMD,    SD2_CLK,    SD2_MMC_PU_CTRL,    SPI2_CLK,    SPI2_MOSI,    SPI2_MISO,    SPI2_SS0,    UH1_OVR,    SPI2_SS1,    UH1_PWR,    U3CE_DSR_B,    U3CE_RI_B,    U3CE_DCD_B,    U3CE_DTR_B,    MDO0,    MDO1,    MDO10,    MDO11,    MDO12,    MDO13,    MDO14,    MDO15,    MDO2,    MDO3,    MDO4,    MDO5,    MDO6,    MDO7,    MDO8,    MDO9,    SD1_DAT0,    SD1_DAT1,    SD1_DAT2,    SD1_DAT3,    SD2_DAT0,    SD2_DAT1,    SD2_DAT2,    SD2_DAT3,    SIM_CLK,    SIM_PD,    SIM_RST_B,    SIM_SVEN,    SIM_TRXD,    U3CE_CTS_B,    USB_RXD,     AP_MAX_PIN = WP_B,};enum iopad_group {    /* IOMUX_AP pad groups */    GROUP10 = 0,    GROUP11,    GROUP12,    GROUP13,    GROUP14,    GROUP15,    GROUP16,    GROUP17,    GROUP18,    GROUP19,    GROUP20,    GROUP21,    GROUP22,    GROUP23,    GROUP24,    GROUP25,    GROUP26,    GROUP27,    GROUP28,    GROUP29,    GROUP30,    GROUP31,    GROUP32,    GROUP33,    GROUP34,    GROUP35,    GROUP36,    GROUP37,    GROUP38,    GROUP39,    GROUP40,    GROUP41,    GROUP42,    GROUP43,    GROUP44,    GROUP45,    GROUP46,    GROUP47,    GROUP48,    GROUP49,    GROUP50,    GROUP51,    GROUP52,    GROUP53,    GROUP54,    GROUP55,    GROUP56,    GROUP57,    GROUP58,        /* IOMUX_COM pad groups */        GROUP1,    GROUP2,    GROUP3,    GROUP4,    GROUP5,    GROUP6,    GROUP7,    GROUP8,    GROUP9,    GROUP59,    GROUP60,    GROUP61,    GROUP62,    GROUP63,    GROUP64,    GROUP65,    GROUP66,    GROUP67,    GROUP68,    GROUP69,    GROUP70,    GROUP71,    GROUP73,    GROUP74,    GROUP75,    GROUP99,    GROUP100,    GROUP101,    GROUP102,    GROUP103,    AP_MAX_PAD = GROUP58,};enum iomux_output_config {        GPIO_MUX1_OUT = (0 << 4),        MUX0_OUT =      (1 << 4),        MUX2_OUT =      (2 << 4),        MUX3_OUT =      (3 << 4),        MUX4_OUT =      (4 << 4),        MUX5_OUT =      (5 << 4),        MUX6_OUT =      (6 << 4),        MUX7_OUT =      (7 << 4),};enum iomux_input_config {        NONE_IN =       0,        GPIO_MUX1_IN =  (1 << 0),        MUX0_IN =       (1 << 1),        MUX2_IN =       (1 << 2),        MUX3_IN =       (1 << 3),};#define MUX_CTL_BIT_LEN     8#define MUX_CTL_BIT_MASK    0xFFenum iomux_pad_config {        SRE_FAST        = (0x1 << 0),        SRE_SLOW        = (0x0 << 0),        DSE_NORMAL      = (0x0 << 1),        DSE_HIGH        = (0x1 << 1),        DSE_MAX         = (0x2 << 1),        DSE_MIN         = (0x3 << 1),        ODE_CMOS        = (0x0 << 3),        ODE_OPEN_DRAIN  = (0x1 << 3),        PKE_ENABLE      = (0x1 << 7),        PKE_DISABLE     = (0x0 << 7),        PUE_ENABLE      = (0x1 << 4),        PUE_KEEPER      = (0x0 << 4),        HYS_SCHMITZ     = (0x1 << 8),        HYS_CMOS        = (0x0 << 8),        DDR_MODE_DDR    = (0x1 << 9),        DDR_MODE_CMOS   = (0x0 << 9),        DDR_INPUT_DDR   = (0x1 << 10),        DDR_INPUT_CMOS  = (0x0 << 10),};/*! * IOMUX_SW_MUX_CTL_REG converts from a pin number to an index for the * SW_MUX_CTL  register.  MXC91131 IOMUX packs 4 pins per SW_MUX_CTL register, * so conversion is  simple divide by 4. */#define IOMUX_SW_MUX_CTL_REG(pin)              ((pin) >> 2)/*! * IOMUX_SW_MUX_CTL_SHIFT converts from a pin number to a shift value used * to reference the SW_MUX_CTL bits assigned to that pin.  MXC91131 * IOMUX packs 4 pins per SW_MUX_CTL register (use % 4 to select pin for * single register) and 8 bits per pin (use multiply by 8) */#define IOMUX_SW_MUX_CTL_SHIFT(pin)            (((pin) % 4) << 3) /*! * IOMUX_SW_MUX_CTL_MASK converts from a pin number to a mask used to isolate * the SW_MUX_CTL register bits assigned to that pin. */#define IOMUX_SW_MUX_CTL_MASK(pin)  \    (0x7F << IOMUX_SW_MUX_CTL_SHIFT(pin))#define IOMUX_PIN_ASSIGN(pIOMUX, pin, in, out) \    pIOMUX[IOMUX_SW_MUX_CTL_REG(pin)] &= (~(IOMUX_SW_MUX_CTL_MASK(pin))); \    pIOMUX[IOMUX_SW_MUX_CTL_REG(pin)] |= ((in | out) << IOMUX_SW_MUX_CTL_SHIFT(pin));#endif /* MXC91131 *//*! * Selection of the UART port depends on the \b UART_PORT value defined in  * \b mxc_nb.h */#ifdef MX21#if (UART_PORT==1)/*! * UART 1 base address */#define MXCNB_UART_BASE         0x1000a000#endif#if (UART_PORT==2)/*! * UART 2 base address  */#define MXCNB_UART_BASE         0x1000b000#endif#else#if (UART_PORT==1)/*! * UART 1 base address */#define MXCNB_UART_BASE         0x43F90000#endif#if (UART_PORT==2) /*! * UART 2 base address  */#define MXCNB_UART_BASE         0x43F94000#endif#endif/*! * This defines the addresses for UART registers for 16 bit access  */#define _reg_URXD       (*((volatile U32 *)(MXCNB_UART_BASE+0x00)))#define _reg_UTXD       (*((volatile U32 *)(MXCNB_UART_BASE+0x40)))#define _reg_UCR1       (*((volatile U32 *)(MXCNB_UART_BASE+0x80)))#define _reg_UCR2       (*((volatile U32 *)(MXCNB_UART_BASE+0x84)))#define _reg_UCR3       (*((volatile U32 *)(MXCNB_UART_BASE+0x88)))#define _reg_UCR4       (*((volatile U32 *)(MXCNB_UART_BASE+0x8C)))#define _reg_UFCR       (*((volatile U32 *)(MXCNB_UART_BASE+0x90)))#define _reg_USR1       (*((volatile U32 *)(MXCNB_UART_BASE+0x94)))#define _reg_USR2       (*((volatile U32 *)(MXCNB_UART_BASE+0x98)))#define _reg_UESC       (*((volatile U32 *)(MXCNB_UART_BASE+0x9C)))#define _reg_UTIM       (*((volatile U32 *)(MXCNB_UART_BASE+0xA0)))#define _reg_UBIR       (*((volatile U32 *)(MXCNB_UART_BASE+0xA4)))#define _reg_UBMR       (*((volatile U32 *)(MXCNB_UART_BASE+0xA8)))#define _reg_UBRC       (*((volatile U32 *)(MXCNB_UART_BASE+0xAC)))#ifdef MX21#define _reg_UTS       (*((volatile U32 *)(MXCNB_UART_BASE+0xB4)))#endif/*! * Mask to check Tx buffer empty */#define TXFE_MASK               0x4000  /*! * Mask to check receive data ready */#define RDR_MASK                0x0001  /*! * UART BRM register value */#define MXC_UART_UBMR           0x1FBC /*! * This defines the External UART Specific values */#ifdef MX21#define BASE                             0xCC000000#define EXT_UART_BASE                   (BASE + 0x200000)#else#define BASE                             0xB4000000#define EXT_UART_BASE                   (BASE + 0x00010000)#endif #if UART_BAUD_RATE==9600#define EXT_SERIAL_BAUD_MSB        0x00#define EXT_SERIAL_BAUD_LSB        0x60#define MXC_UART_UBIR              0x5F      #endif #if UART_BAUD_RATE==19200#define EXT_SERIAL_BAUD_MSB        0x00#define EXT_SERIAL_BAUD_LSB        0x30#define MXC_UART_UBIR              0xC0      #endif #if UART_BAUD_RATE==38400#define EXT_SERIAL_BAUD_MSB        0x00#define EXT_SERIAL_BAUD_LSB        0x18#define MXC_UART_UBIR              0x17F      #endif #if UART_BAUD_RATE==57600#define EXT_SERIAL_BAUD_MSB        0x00#define EXT_SERIAL_BAUD_LSB        0x10#define MXC_UART_UBIR              0x23F      #endif #if UART_BAUD_RATE==115200#define EXT_SERIAL_BAUD_MSB              0x00#define EXT_SERIAL_BAUD_LSB              0x08#define MXC_UART_UBIR              0x47F      #endif #if  (UART_PORT==1)#define EXT_SERIAL_BASE                 (EXT_UART_BASE + 0x0000) // port A#endif#if (UART_PORT==2)#define EXT_SERIAL_BASE                 (EXT_UART_BASE + 0x0010) // port B#endif#endif/*! * This defines the addresses for External UART registers  */#ifdef MXC91331#define _reg_RHR        (*((volatile U16 *)(EXT_SERIAL_BASE+0x00)))#define _reg_THR        (*((volatile U16 *)(EXT_SERIAL_BASE+0x00)))#define _reg_DLL        (*((volatile U16 *)(EXT_SERIAL_BASE+0x00)))#define _reg_IER        (*((volatile U16 *)(EXT_SERIAL_BASE+0x02)))#define _reg_DLM        (*((volatile U16 *)(EXT_SERIAL_BASE+0x02)))#define _reg_IIR        (*((volatile U16 *)(EXT_SERIAL_BASE+0x04)))#define _reg_FCR        (*((volatile U16 *)(EXT_SERIAL_BASE+0x04)))#define _reg_AFR        (*((volatile U16 *)(EXT_SERIAL_BASE+0x04)))#define _reg_LCR        (*((volatile U16 *)(EXT_SERIAL_BASE+0x06)))#define _reg_MCR        (*((volatile U16 *)(EXT_SERIAL_BASE+0x08)))#define _reg_MCR_A      (*((volatile U16 *)(EXT_SERIAL_BASE+0x08)))#define _reg_MCR_B      (*((volatile U16 *)(EXT_SERIAL_BASE+0x08)))#define _reg_LSR        (*((volatile U16 *)(EXT_SERIAL_BASE+0x0A)))#define _reg_MSR        (*((volatile U16 *)(EXT_SERIAL_BASE+0x0C)))#define _reg_SCR        (*((volatile U16 *)(EXT_SERIAL_BASE+0x0E)))#else#define _reg_RHR        (*((volatile U8 *)(EXT_SERIAL_BASE+0x00)))#define _reg_THR        (*((volatile U8 *)(EXT_SERIAL_BASE+0x00)))#define _reg_DLL        (*((volatile U8 *)(EXT_SERIAL_BASE+0x00)))#define _reg_IER        (*((volatile U8 *)(EXT_SERIAL_BASE+0x01)))#define _reg_DLM        (*((volatile U8 *)(EXT_SERIAL_BASE+0x01)))#define _reg_IIR        (*((volatile U8 *)(EXT_SERIAL_BASE+0x02)))#define _reg_FCR        (*((volatile U8 *)(EXT_SERIAL_BASE+0x02)))#define _reg_AFR        (*((volatile U8 *)(EXT_SERIAL_BASE+0x02)))#define _reg_LCR        (*((volatile U8 *)(EXT_SERIAL_BASE+0x03)))#define _reg_MCR        (*((volatile U8 *)(EXT_SERIAL_BASE+0x04)))#define _reg_MCR_A      (*((volatile U8 *)(EXT_SERIAL_BASE+0x04)))#define _reg_MCR_B      (*((volatile U8 *)(EXT_SERIAL_BASE+0x04)))#define _reg_LSR        (*((volatile U8 *)(EXT_SERIAL_BASE+0x05)))#define _reg_MSR        (*((volatile U8 *)(EXT_SERIAL_BASE+0x06)))#define _reg_SCR        (*((volatile U8 *)(EXT_SERIAL_BASE+0x07)))#endif /* MXC91331 *//*! * The line status register bits. */#define SIO_LSR_DR      0x01            /* data ready */#define SIO_LSR_THRE    0x20            /* transmitter holding register empty *//*! * The line control register bits.  */#define SIO_LCR_WLS0   0x01             /*word length select bit 0 */#define SIO_LCR_WLS1   0x02             /* word length select bit 1 */#define SIO_LCR_DLAB   0x80             /* divisor latch access bit */#if UART_OUTPUT==INT_UART#define mxcnb_outstring         mxcnb_uart_putstring   #define mxcnb_getstring         mxcnb_uart_getstring   #define mxcnb_getdata           mxcnb_uart_getdata#define mxcnb_putdata           mxcnb_uart_putdata#define mxcnb_dataready         mxcnb_uart_dataready#define mxcnb_gethex            mxcnb_uart_gethex#define mxcnb_puthex            mxcnb_uart_puthex#else#define mxcnb_outstring         ext_uart_write      #define mxcnb_getstring         ext_uart_read         #define mxcnb_getdata           ext_uart_getc#define mxcnb_putdata           ext_uart_putc  #define mxcnb_dataready         ext_uart_dataready#define mxcnb_gethex             ext_uart_gethex#define mxcnb_puthex             ext_uart_puthex#endif /* MXC_NB_UART_H */