/* * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA *//*! * @file mxc_nb_init.c *  * @brief This file contains the initialization code of the basic hardware  * required for NANDboot to boot the Linux kernel *  * @ingroup NANDboot */#include "mxc_nb.h"#include "mxc_nb_uart.h"#define MSDELAY(x)      ((x)*1000)/*! * Register defines for Watchdog timer */#define _reg_WDOG_WCR           (*((volatile U16 *)(WDOG_BASE + 0x00)))#define _reg_WDOG_WSR           (*((volatile U16 *)(WDOG_BASE + 0x02)))#define _red_WDOG_WRSR          (*((volatile U16 *)(WDOG_BASE + 0x04)))/*! * CSPI defines */#define CSPI2_BASE_ADDR		0x50010000#define CSPI2_RXDATAREG   	(CSPI2_BASE_ADDR + 0x00)#define CSPI2_TXDATAREG   	(CSPI2_BASE_ADDR + 0x04)#define CSPI2_CONTROLREG  	(CSPI2_BASE_ADDR + 0x08)#define CSPI2_INTREG      	(CSPI2_BASE_ADDR + 0x0C)#define CSPI2_DMAREG      	(CSPI2_BASE_ADDR + 0x10)#define CSPI2_STATREG     	(CSPI2_BASE_ADDR + 0x14)#define CSPI2_PERIODREG   	(CSPI2_BASE_ADDR + 0x18)#define CSPI2_TESTREG     	(CSPI2_BASE_ADDR + 0x1C)#define _reg_CSPI(a) 		(*((volatile unsigned long *) a))#define MIN_DATA_RATE_SHIFT         2#define DATA_RATE_SHIFT            16#define MODE_MASTER_SLAVE_SHIFT     1#define EXCHANGE_BIT_SHIFT          2#define SMC_CONTROL_SHIFT           3#define STATE_ENABLE_DISABLE_SHIFT  0#define SS_POLARITY_SHIFT           7#define SS_WAVEFORM_SHIFT           6#define PHASE_SHIFT                 5#define POLARITY_SHIFT              4#define DATA_RATE_MASK            0x7#define INTERRUPT_IRQ_BIT_SHIFT     9#define INTERRUPT_IRQ_BIT_SHIFT_0_7 8#define BIT_COUNT_SHIFT             8#define RDY_CONTROL_SHIFT          20#define CHIP_SELECT_SHIFT          24#define BIT_COUNT_MASK          0x01f#define BIT_COUNT_SHIFT_0_5        20#define RDY_CONTROL_SHIFT_0_5       8#define CHIP_SELECT_SHIFT_0_5      12#define BIT_COUNT_MASK_0_5     0x0fff#define BIT_COUNT_SHIFT_0_0             0#define RDY_CONTROL_SHIFT_0_0         12#define CHIP_SELECT_SHIFT_0_0      19#define BIT_COUNT_MASK_0_0          0x01f#define INTERRUPT_IRQ_BIT_SHIFT_0_0 18#define MODIFY_REGISTER_32(a,b,c) c = ( ( c & (~(a)) ) | b )/*! * This is the initialization function for Watchdog Timer. */#if WDOG_EN==1void mxcnb_wd_init(void){#if UNIT_TEST        U32* debug_addr = DEBUG_ADDR2;#endif          _reg_WDOG_WCR |= WDOG_TIMEOUT;                  /* Set WRE (4th bit) and SRS (5th bit) to 0 to generate          * reset signal on timeout        */        _reg_WDOG_WCR &= ~0x0018;                 _reg_WDOG_WCR |= 0x0004; /* Enable Watchdog Timer */#if UNIT_TEST        if (!(_reg_WDOG_WCR & 0x0400)) {                *(debug_addr++) = 0x50;         /* error */        } else {                *(debug_addr++) = 0x70;         /* success */        }        if ( _reg_WDOG_WCR & 0x0018 ) {                *(debug_addr++) = 0x51;         /* error */        } else {                *(debug_addr++) = 0x71;         /* success */        }        if (!(_reg_WDOG_WCR & 0x0004)) {                *(debug_addr++) = 0x52;         /* error */        } else {                *(debug_addr++) = 0x72;         /* success */        }#endif }#elsevoid mxcnb_wd_init(void){}#endif/*! * This function is used to service the Watchdog Timer before it gets timeout. */void mxcnb_wd_reset(void){        if( _reg_WDOG_WSR & 0x0004) { /* service only if WDOG enabled */                _reg_WDOG_WSR = 0x5555;                _reg_WDOG_WSR = 0xAAAA;        }}#ifdef MX21/*!*    Init Mx2 Hardware. *    Init CS0,CS1,CS3*/void mx2_init(){    	 int dummy,reg;		    // burst-flash initialization    //comment # CS0 Initialization (Async Mode)     //comment # 32-bit, ?? wait states              //setmem 0xDF001000 0x00003E00 32//setmem 0xDF001004 0x00000E01 32	_reg_WEIM_CSU(0) = 0x00003E00;	_reg_WEIM_CSL(0) = 0x00000E01; //comment # Setting for Memory Map IO Port//comment # CS1 Initialization (Async Mode)//comment # 16-bit, D0..15, ?? wait states//setmem 0xDF001008 0x00002000 32//setmem 0xDF00100C 0x11118501 32	_reg_WEIM_CSU(1)=0x00002000 ;	_reg_WEIM_CSL(1)=0x11118501 ;//comment # CS3 Initialization (Async Mode)//comment # 32-bit, ?? wait states//setmem 0xDF001018 0x00003E00 32//setmem 0xDF00101C 0x11110601 32	_reg_WEIM_CSU(3)=0x00003E00 ;	_reg_WEIM_CSL(3)=0x11110601 ;//comment # Config MUX for pin PF18->CS1//comment # Clear PTF_GIUSE //setmem 0x10015520 0x00000000 32	_reg_GPIO_GIUS(GPIOF)&=~0x40000;//comment # Clear PTF_GPR//setmem 0x10015538 0x00000000 32	_reg_GPIO_GPR(GPIOF)&=~0x40000;//comment # FMCR Register//comment # Select CS3/CSD0 Pin as CS3 only.//setmem 0x10027814 0xFFFFFFC9 32	_reg_SYS_FMCR=0xFFFFFFC9;   // Initialize all peripheral in AIPI1 PSR[1:0] => 10=32bit, 01=16bit, 00=8bit	 _reg_AIPI1_PSR0 = 0x00040304;	 _reg_AIPI1_PSR1 = 0xFFFBFCFB;    // Initialize all peripheral in AIPI1 PSR[1:0] => 10=32bit, 01=16bit, 00=8bit	_reg_AIPI2_PSR0 = 0x0;	_reg_AIPI2_PSR1 = 0xFFFFFFFF; 	//write to the FMCR [31:24] (CLKMODE[1:0]) in order to get the write enable signal active 	_reg_SYS_FMCR |= 0xAA000000;    }void mx21_module_init(){	//comment ### Master Priority Register for Slave Port 3	// Keep LCDC as the highest priority	_reg_SYS_PCSR = 0;	_reg_MAX_SLV_MPR(3) = 0x00123056;	_reg_MAX_SLV_SGPCR(3) = 0;//comment # enable user mode CSI access//setmem 0x10027818 0x6000e 32        _reg_SYS_GPCR = 0x6000e;}#endif /*end of MX21 *//*! * This function waits for input from user for few sec(6sec) * * @param       timeout   indicates the timeout or input from user *              1 -> Time out occured *              0->  Input from user * */int  mxcnb_timeout(int timeout){        unsigned int j;        for (j = 0; j < MSDELAY(timeout); j++) {                 udelay(10);                 if(mxcnb_dataready()) {                         return 0;                 }       }       return 1;}