/*****************************************************************************
* File name :     C6711_EMIF.c
* Description:
******************************************************************************/
#ifndef MASTER_FILE
#define C6711_GLOBALS
//#include "includes.h"
#endif
#include "c6711dsk.h"
#include "EMIF.H"

/*------------------------------------------------------------------------*
* Image Processing Board includes 2 L4316064 devices =>16MB SDRAM        
*   64Mb (16-bit x 4 banks x 1M)   parts = 8MB / part                     
*   EMIF_SDCTL=0x57116000 or 0x57227000                                               *
*   EMIF_SDEXT=0x54529 (Hitachi 0x54509)                    
*-------------------------------------------------------------------------*/

/******************************************************************************
* Function    : emif_init()
* description : Config EMIF Registers
*  Input      : None
*  Output     : None
******************************************************************************/
void emif_init()
{ 

//  CSR=0x100;                           /* Disable all interrupts              */
  IER=1;                               /* Disable all interrupts except NMI   */
  ICR=0xffff;                          /* Clear all pending interrupts        */
 
  *(unsigned volatile int *)EMIF_GBLCTL = 0x3338; /* EMIF global control   */
  *(unsigned volatile int *)EMIF_CECTL0 = 0x30;   /* EMIF CE0control       */
  *(unsigned volatile int *)EMIF_CECTL1 = CE1_8; /* EMIF CE1control       */
  *(unsigned volatile int *)EMIF_CECTL2 = 0x11E1CB22;//;FFFFFF23 /* CE2-32bit async on daughtercard*/
  *(unsigned volatile int *)EMIF_CECTL3 = 0x11E1C722;//FFFFFF23; /* CE3-32bit async on daughtercard*/
  
/* MT48LC4M16A2-10 use the following parameter: EMIF_SDCTRL=0x57227000 */  
  *(unsigned volatile int *)EMIF_SDCTL = 0x07126000;//57116000; 
  *(unsigned volatile int *)EMIF_SDTIM = 0x61a;    /* EMIF SDRM refresh period */
  *(unsigned volatile int *)EMIF_SDEXT = 0x54529;  /* EMIF SDRM extension      */
  
  
/*************************************************************************
* The IPB includes 2 L43L16064 devices = 8MB SDRAM,16MByte totally       *
* For these devices use the following parameter:                         *
*   EMIF_SDCTRL=0x07126000                                               *
*   EMIF_SDRP                                                            *
*   EMIF_SDEXT                                                           *
*************************************************************************/
 
}

/******************************************************************************
* Function    : ce1_config()
* ARGUMENTS   : cectl1 is EMIF CE1 space control register (CECTL1) configure. 
* description : Config EMIF_CECTL1 Registers: 
*                CE1_8=0xffffff03    set CE1 as 8bit async 
*                CE1_32=0xffffff23   set CE1 as 32bit async 
******************************************************************************/
void ce1_config(int cectl1)
{
 *(unsigned volatile int *)EMIF_CECTL1 = cectl1;
}


/* END OF FILE */