/******************************************************************************/
/*  CACHE.H - TMS320C6711 Peripheral Support Library Cache Support            */
/*                                                                            */
/*     This file provides the header for the DSP's Cache support.             */
/******************************************************************************/
#ifndef _CACHE_H_
#define _CACHE_H_


/*----------------------------------------------------------------------------*/
/* INCLUDES                                                                   */
/*----------------------------------------------------------------------------*/
#ifndef MASTER_FILE
#define C6711_GLOBALS
#include "C6711_CPU.H"
#endif

/*----------------------------------------------------------------------------*/
/*                                 DEFINES                                    */
/*----------------------------------------------------------------------------*/

/* Define  Cache Registers */
#define CCFG            0x1840000   /* Address of Cache config reg          */
#define L2FBAR          0x1844000   /* Address of L2 flush base address reg.*/
#define L2FWC           0x1844004   /* Address of L2 flush word count reg.  */
#define L2CBAR          0x1844010   /* Address of L2 clean base address reg.*/
#define L2CWC           0x1844014   /* Address of L2 clean word count reg.  */
#define L1PFBAR         0x1844020   /* Address of L1P flush base address reg.*/
#define L1PFWC          0x1844024   /* Address of L1P flush word count reg. */
#define L1DFBAR         0x1844030   /* Address of L1D flush base address reg.*/
#define L1DFWC          0x1844034   /* Address of L1D flush word count reg. */
#define L2FULSH         0x1845000   /* Address of L2 flush reg.             */
#define L2CLEAN         0x1845004   /* Address of L2 clean reg.             */
#define MAR0            0x1848200   /* Control CE0 range 0x80000000~0x80FFFFFF */
#define MAR1            0x1848204   /* Control CE0 range 0x81000000~0x81FFFFFF */
#define MAR2            0x1848208   /* Control CE0 range 0x82000000~0x82FFFFFF */
#define MAR3            0x184820C   /* Control CE0 range 0x83000000~0x83FFFFFF */
#define MAR4            0x1848240   /* Control CE1 range 0x90000000~0x90FFFFFF */
#define MAR5            0x1848244   /* Control CE1 range 0x91000000~0x91FFFFFF */
#define MAR6            0x1848248   /* Control CE1 range 0x92000000~0x92FFFFFF */
#define MAR7            0x184824C   /* Control CE1 range 0x93000000~0x93FFFFFF */
#define MAR8            0x1848280   /* Control CE2 range 0xA0000000~0xA0FFFFFF */
#define MAR9            0x1848284   /* Control CE2 range 0xA1000000~0xA1FFFFFF */
#define MAR10           0x1848288   /* Control CE2 range 0xA2000000~0xA2FFFFFF */
#define MAR11           0x184828C   /* Control CE2 range 0xA3000000~0xA3FFFFFF */
#define MAR12           0x18482C0   /* Control CE3 range 0xB0000000~0xB0FFFFFF */
#define MAR13           0x18482C4   /* Control CE3 range 0xB1000000~0xB1FFFFFF */
#define MAR14           0x1848208   /* Control CE3 range 0xB2000000~0xB2FFFFFF */
#define MAR15           0x184820C   /* Control CE3 range 0xB3000000~0xB3FFFFFF */

   /* Address of Cache config reg (CCFG) Bitfield */
#define L2MODE             0  /*L2 Operation Mode*/
#define L2MODE_SZ          3
#define ID                 8  /*Invalidate L1D   */
#define IP                 9  /*L1P operation    */

/*----------------------------------------------------------------------------*/
/*                        MACROS  FUNCTIONS                                   */
/*----------------------------------------------------------------------------*/
#define CACHE_ENABLE()     {CSR &= 0xFFFFFF1F; CSR |= 0x40;}

#define CACHE_DISABLE()    {CSR &= 0xFFFFFF1F;}

#define CACHE_FREEZE()     {CSR &= 0xFFFFFF1F; CSR |= 0x60;}

#define CACHE_BYPASS()     {CSR &= 0xFFFFFF1F; CSR |= 0x80;}

#define CACHE_FLUSH()      {CACHE_DISABLE(); CACHE_ENABLE();}

#endif  /*_CACHE_H*/