/******************************************************************************/
/*  INTERRUPTS.H - TMS320C6711 Peripheral Support Library Interrupt Support           */
/*                                                                            */
/*     This file provides the header for the DSP's interrupt support.         */
/******************************************************************************/

/*----------------------------------------------------------------------------*/
/* INCLUDES                                                                   */
/*----------------------------------------------------------------------------*/
#ifndef MASTER_FILE
#define C6711_GLOBALS
#include "C6711_CPU.H"
#endif

#ifndef _INTR_H_
#define _INTR_H_

/*----------------------------------------------------------------------------*/
/*                                 DEFINES                                    */
/*----------------------------------------------------------------------------*/
/* Define Interrupt Registers */
#define IMH             0x19c0000   /* Address of Interrupt Multiplexer High */
#define IML             0x19c0004   /* Address of Interrupt Multiplexer Low  */
#define EXTPOL          0x19c0008   /* Address External Interrupt Polarity   */

/* Interrupt Enable Register (IER) */
#define NMIE                  1
#define IE4                   4
#define IE5                   5
#define IE6                   6
#define IE7                   7
#define IE8                   8
#define IE9                   9
#define IE10                 10
#define IE11                 11
#define IE12                 12
#define IE13                 13
#define IE14                 14
#define IE15                 15

/* Interrupt Flag Register (IFR) */
#define NMIF                  1
#define IF4                   4
#define IF5                   5
#define IF6                   6
#define IF7                   7
#define IF8                   8
#define IF9                   9
#define IF10                 10
#define IF11                 11
#define IF12                 12
#define IF13                 13
#define IF14                 14
#define IF15                 15

/* Interrupt Set register (ISR)   IS[4:15]=4:15  */
/* Interrupt Clear Register (ICR) IC[4:15}=4:15  */

/* Interrupt Service Table Pointer (ISTP) */
#define ISTB                 10
#define ISTB_SZ              22
#define HPEINT                5
#define HPEINT_SZ             5

/* INTERRUPT SELECTOR REGISTERS */
#define INTR_MULTIPLEX_HIGH_ADDR     0x019C0000
#define INTR_MULTIPLEX_LOW_ADDR      0x019C0004
#define EXTERNAL_INTR_POL_ADDR       0x019C0008

 /*Interrupt Multiplexer Register Low (MUXL) Bitfield*/
#define INTSEL_SZ           4  /**/
#define INTSEL4             0  /**/
#define INTSEL5             5  /**/
#define INTSEL6            10  /**/
#define INTSEL7            16  /**/
#define INTSEL8            21  /**/
#define INTSEL9            26  /**/

/*Interrupt Multiplexer Register High (MUXH) Bitfield*/
#define INTSEL10            0  /**/
#define INTSEL11            5  /**/
#define INTSEL12           10  /**/
#define INTSEL13           16  /**/
#define INTSEL14           21  /**/
#define INTSEL15           26  /**/

/* External Interrupt Polarity Register(EXTPOL) Bitfield */
#define XIP4                0  /**/
#define XIP5                1  /**/
#define XIP6                2  /**/
#define XIP7                3  /**/

/* CPU Interrupt Numbers       */
#define CPU_INT_RST          0x00
#define CPU_INT_NMI          0x01
#define CPU_INT_RSV1         0x02
#define CPU_INT_RSV2         0x03
#define CPU_INT4             0x04
#define CPU_INT5             0x05
#define CPU_INT6             0x06
#define CPU_INT7             0x07
#define CPU_INT8             0x08
#define CPU_INT9             0x09
#define CPU_INT10            0x0A
#define CPU_INT11            0x0B
#define CPU_INT12            0x0C
#define CPU_INT13            0x0D
#define CPU_INT14            0x0E
#define CPU_INT15            0x0F

/* Interrupt Selection Numbers of Interrupt Events  */
#define ISN_DSPINT           0x00  /*Host processor to DSP interrupt*/
#define ISN_TINT0            0x01  /*Timer 0 interrupt        */
#define ISN_TINT1            0x02  /*Timer 1 interrupt         */
#define ISN_SD_INT           0x03  /*EMIF SDRAM timer interrupt*/     
#define ISN_EXT_INT4         0x04  /*External interrupt pin 4  */
#define ISN_EXT_INT5         0x05  /*External interrupt pin 5  */
#define ISN_EXT_INT6         0x06  /*External interrupt pin 6  */
#define ISN_EXT_INT7         0x07  /*External interrupt pin 7  */
#define ISN_EDMA_INT         0x08  /*EDMA channel 0 interrupt  */
#define ISN_XINT0            0x0C  /*McBSP 0 transmit interrupt*/
#define ISN_RINT0            0x0D  /*McBSP 0 receive interrupt */
#define ISN_XINT1            0x0E  /*McBSP 1 transmit interrupt*/
#define ISN_RINT1            0x0F  /*McBSP 1 receive interrupt */

#define IML_SEL              0x00       /* Interrupt Multiplexer Low Select   */
#define IMH_SEL              0x01       /* Interrupt Multiplexer High Select  */

/* INT4:  EXT_INT4  (00100B)  INT5: EXT_INT5  (00101B)  */
/* INT6:  EXT_INT6  (00110B)  INT7: EXT_INT7  (00111B)  */
/* INT8:  EDMA_INT  (01000B)  INT9: RINT0     (01101B)  */
/* INT10: SDINT     (00100B)  INT11:RINT1     (01111B)  */
/* INT12: DEFAULT   (01011B)  INT13:DSPINT    (00000B)  */
/* INT14: TINT0     (00001B)  INT15:TINT1     (00010B)  */
#define IML_RESET_VAL        0x250718A4
#define IMH_RESET_VAL        0x08202DE4

/*----------------------------------------------------------------------------*/
/*          MACRO FUNCTIONS                                                   */
/*----------------------------------------------------------------------------*/

/*----------------------------------------------------------------------------*/
/* INTR_GLOBAL_ENABLE - enables all masked interrupts by setting the GIE      */
/*              bit (bit 0) in the CSR                                        */
/*----------------------------------------------------------------------------*/
#define INTR_GLOBAL_ENABLE()   SET_REG_BIT(CSR, GIE)

/*----------------------------------------------------------------------------*/
/* INTR_GLOBAL_DISABLE - disables all masked interrupts by clearing the GIE   */
/*               (bit 0) in the CSR.                                          */
/*----------------------------------------------------------------------------*/
#define INTR_GLOBAL_DISABLE()   RESET_REG_BIT(CSR, GIE)

/*----------------------------------------------------------------------------*/
/* INTR_ENABLE - enable interrupt by setting flag in IER                      */
/*----------------------------------------------------------------------------*/
#define INTR_ENABLE(bit)    SET_REG_BIT(IER,bit) 

/*----------------------------------------------------------------------------*/
/* INTR_DISABLE - disable interrupt by clearing flag in IER                   */
/*----------------------------------------------------------------------------*/
#define INTR_DISABLE(bit)    RESET_REG_BIT(IER,bit) 

/*----------------------------------------------------------------------------*/
/* INTR_CHECK_FLAG - checks status of indicated interrupt bit in IFR          */
/*----------------------------------------------------------------------------*/
#define INTR_CHECK_FLAG(bit)  (IFR & MASK_BIT(bit) ? 1 : 0)

/*----------------------------------------------------------------------------*/
/* INTR_SET_FLAG - manually sets indicated interrupt by writing to ISR        */
/*----------------------------------------------------------------------------*/
#define INTR_SET_FLAG(bit)    (ISR = MASK_BIT(bit))

/*----------------------------------------------------------------------------*/
/* INTR_CLR_FLAG - manually clears indicated interrupt by writing 1 to ICR    */
/*----------------------------------------------------------------------------*/
#define INTR_CLR_FLAG(bit)    (ICR = MASK_BIT(bit))

/*----------------------------------------------------------------------------*/
/* INTR_SET_MAP  - maps a CPU interrupt specified by intr to the interrupt src*/
/*            specified by val.  Sel is used to select between the low and    */
/*            high interrupt_multiplexer registers.                           */
/*----------------------------------------------------------------------------*/
#define INTR_SET_MAP(intsel,val,sel) \
        (sel ? LOAD_FIELD(INTR_MULTIPLEX_HIGH_ADDR,val,intsel,INTSEL_SZ) : \
               LOAD_FIELD(INTR_MULTIPLEX_LOW_ADDR, val,intsel,INTSEL_SZ ))

/*----------------------------------------------------------------------------*/
/* INTR_GET_ISN - returns the ISN value in the selected Interrupt Multiplexer */
/*                register for the interrupt selected by intsel               */
/*----------------------------------------------------------------------------*/
#define INTR_GET_ISN(intsel,sel) \
        (sel ? GET_FIELD(INTR_MULTIPLEX_HIGH_ADDR,intsel,INTSEL_SZ) : \
               GET_FIELD(INTR_MULTIPLEX_LOW_ADDR, intsel,INTSEL_SZ))

/*----------------------------------------------------------------------------*/
/* INTR_MAP_RESET - resets the interrupt multiplexer maps to their default val*/
/*----------------------------------------------------------------------------*/
#define INTR_MAP_RESET() \
        { REG_WRITE (INTR_MULTIPLEX_HIGH_ADDR,IMH_RESET_VAL); \
          REG_WRITE (INTR_MULTIPLEX_LOW_ADDR, IML_RESET_VAL); }

/*----------------------------------------------------------------------------*/
/* INTR_EXT_POLARITY - assigns external interrupt external priority.          */
/*                    val = 0 (normal), val = 1 (inverted)                    */
/*----------------------------------------------------------------------------*/
#define INTR_EXT_POLARITY(bit,val) \
        {val ? SET_BIT(EXTERNAL_INTR_POL_ADDR,bit) : \
              RESET_BIT(EXTERNAL_INTR_POL_ADDR,bit)}


/*----------------------------------------------------------------------------*/
/* GLOBAL VARIABLES                                                           */
/*----------------------------------------------------------------------------*/
extern unsigned int istb;
extern unsigned int NMI, RESV1, RESV2;
extern unsigned int Interrupt_4_Handler,  Interrupt_5_Handler;
extern unsigned int Interrupt_6_Handler,  Interrupt_7_Handler;
extern unsigned int Interrupt_8_Handler,  Interrupt_9_Handler;
extern unsigned int Interrupt_10_Handler, Interrupt_11_Handler;
extern unsigned int Interrupt_12_Handler, Interrupt_13_Handler;
extern unsigned int Interrupt_14_Handler, Interrupt_15_Handler;

/*----------------------------------------------------------------------------*/
/*  FUNCTIONS:                                                                */
/*----------------------------------------------------------------------------*/

/* intr_map() - Place isn value in Interrupt Multiplexer Register in INTSEL   */
/*              field indicated by cpu_intr.                                  */
static inline void intr_map(int cpu_intr,int isn)
{
  int intsel;
  int sel;

  if (cpu_intr > CPU_INT9)
    sel=1;
  else
    sel= 0;

  intsel= ((cpu_intr - CPU_INT4) * 5) - (sel * 30);
  if (intsel > INTSEL6)
    intsel++;

 INTR_SET_MAP(intsel,isn,sel);
}


/* intr_isn() - return isn in interrupt selector corresponding to cpu_intr    */
static inline int intr_isn(int cpu_intr)
{

  int intsel;
  int sel;

  if (cpu_intr > CPU_INT9)
    sel= 1;
  else
    sel= 0;

  intsel= ((cpu_intr - CPU_INT4) * 5) - (sel * 30);
  if (intsel > INTSEL6)
    intsel++;

  return(INTR_GET_ISN(intsel,sel));
}

/* intr_get_cpu_intr() - return cpu interrupt corresponding to isn in         */
/*                       interrupt selector register.  If the isn is not      */
/*                       mapped, return -1                                    */
static inline int intr_get_cpu_intr(int isn)
{
  int i;
  for (i= CPU_INT4;i<=CPU_INT15;i++)
  {
    if (intr_isn(i) == isn)
      return(i);
  }
  return(-1);
}


#endif /* _INTR_H_ */