/******************************************************************************/
/*  QDMA.H - TMS320C6711 Peripheral Support Library QDMA Support              */
/*                                                                            */
/*     This file provides the header for the DSP's QDMA support.              */
/******************************************************************************/
#ifndef _QDMA_H_
#define _QDMA_H_


/*----------------------------------------------------------------------------*/
/* INCLUDES                                                                   */
/*----------------------------------------------------------------------------*/
#ifndef MASTER_FILE
#define C6711_GLOBALS
#include "C6711_CPU.H"
#endif

/*----------------------------------------------------------------------------*/
/*                                 DEFINES                                    */
/*----------------------------------------------------------------------------*/

/* Define QDMA Memory Mapped Registers */
#define QDMA_OPT		0x02000000	/* Address of QDMA options register     */
#define QDMA_SRC		0x02000004	/* Address of QDMA SRC address register */
#define QDMA_CNT		0x02000008	/* Address of QDMA counts register      */
#define QDMA_ELECNT     0           /* The number of elements per frame                  */
#define QDMA_FRMCNT     16          /* The number of frames/arrays per block minus one   */
#define QDMA_DST		0x0200000C	/* Address of QDMA DST address register */
#define QDMA_IDX		0x02000010	/* Address of QDMA index register       */
#define QDMA_ELEIDX     0           /* The address offset of elements within a frame      */
#define QDMA_FRMIDX     16          /* The address offset of frames/arrays within a block */
 
/* Define QDMA Pseudo Registers */
#define QDMA_S_OPT		0x02000020	/* Address of QDMA options register     */
#define QDMA_S_SRC		0x02000024	/* Address of QDMA SRC address register */
#define QDMA_S_CNT		0x02000028	/* Address of QDMA counts register      */
#define QDMA_S_DST		0x0200002C	/* Address of QDMA DST address register */
#define QDMA_S_IDX		0x02000030	/* Address of QDMA index register       */

/*  Define QDMA Option Parameter (OPT) Bitfield*/
#define OPT_TCC             16  /* Transfer complete code          */
#define OPT_TCC_SZ          4   
#define OPT_TCINT           20  /* Transfer complete interrupt     */
#define OPT_DUM             21  /* Destination address update mode */
#define OPT_DUM_SZ          2
#define OPT_2DD             23  /* Destination dimension           */
#define OPT_SUM             24  /* Source address update mode      */
#define OPT_SUM_SZ          2  
#define OPT_2DS             26  /* Source dimension                */
#define OPT_ESIZE           27  /* Element size                    */
#define OPT_ESIZE_SZ        2   
#define OPT_PRI             29  /* Priority levels for QDMA events */
#define OPT_PRI_SZ          3   /*    001b Level1: high priority   */
                                /*    010b Level2: low priority    */ 

/*----------------------------------------------------------------------------*/
/*     MACRO FUNCTIONS                                                        */
/*----------------------------------------------------------------------------*/

/* Attention: Each of the QDMA registers is write only. Reads of the QDMA     */
/*            registers will return invalid data.                             */
/*            Access to each QDMA registers is limited to 32-bits only.       */
/*            Halfword and byte writes to the QDMA registers will write the   */
/*            entire register, and thus should be avoided.                    */


 /* Assign QDMA Options Parameter (OPT) bitfields */               
#define QDMA_SRC_1D(s)               RESET_BIT((QDMA_OPT+32*s),OPT_2DS) 
#define QDMA_SRC_2D(s)               SET_BIT((QDMA_OPT+32*s), OPT_2DS)
#define QDMA_DST_1D(s)               RESET_BIT((QDMA_OPT+32*s),OPT_2DD) 
#define QDMA_DST_2D(s)               SET_BIT((QDMA_OPT+32*s), OPT_2DD)
#define QDMA_TCINT_ENABLE(s)         SET_BIT((QDMA_OPT+32*s), OPT_TCINT)
#define QDMA_TCINT_DISABLE(s)        RESET_BIT((QDMA_OPT+32*s),OPT_TCINT)
#define QDMA_TCC_WRITE(tcc,s)\
        LOAD_FIELD((QDMA_OPT+32*s),tcc,OPT_TCC,OPT_TCC_SZ)
#define QDMA_SUM_WRITE(sum,s)\
        LOAD_FIELD((QDMA_OPT+32*s),sum,OPT_SUM,OPT_SUM_SZ)
#define QDMA_DUM_WRITE(dum,s)\
        LOAD_FIELD((QDMA_OPT+32*s),dum,OPT_DUM,OPT_DUM_SZ)
#define QDMA_ESIZE_WRITE(esize,s)\
        LOAD_FIELD((QDMA_OPT+32*s),esize,OPT_ESIZE,OPT_ESIZE_SZ)
#define QDMA_PRI_WRITE(pri,s)\
        LOAD_FIELD((QDMA_OPT+32*S),pri,OPT_PRI,OPT_PRI_SZ)

 /* Assign QDMA Parameter Set */  
#define QDMA_OPT_WRITE(opt,s)      REG_WRITE((QDMA_OPT+32*s),opt)                        
#define QDMA_SRC_WRITE(addr,s)     REG_WRITE((QDMA_SRC+32*s),addr)
#define QDMA_DST_WRITE(addr,s)     REG_WRITE((QDMA_DST+32*s),addr)
#define QDMA_ELECNT_WRITE(elecnt,s)\
        LOAD_FIELD((QDMA_CNT+32*s),elecnt,QDMA_ELECNT,16)
#define QDMA_FRMCNT_WRITE(frmcnt,s)\
        LOAD_FIELD((QDMA_CNT+32*s),frmcnt,QDMA_FRMCNT,16)
#define QDMA_ELEIDX_WRITE(eleidx,s)\
        LOAD_FIELD((QDMA_IDX+32*s),eleidx,QDMA_ELEIDX,16)
#define QDMA_FRMIDX_WRITE(frmidx,s)\
        LOAD_FIELD((QDMA_IDX+32*s),frmidx,QDMA_FRMIDX,16)
        
//#define EDMA_SYNC_ENABLE(chan)    SET_BIT((((1<<chan)&0x0F00)?CCER:EER),chan)
//#define EDMA_SYNC_DISABLE(chan)   RESET_BIT((((1<<chan)&0x0F00)?CCER:EER),chan)

#define QDMA_CHAIN_ENABLE(chan)   SET_BIT(CCER,chan)
#define QDMA_CHAIN_DISABLE(chan)  RESET_BIT(CCER,chan)

#define QDMA_INT_ENABLE(chan)    SET_BIT(CIER,chan)
#define QDMA_INT_DISABLE(chan)   RESET_BIT(CIER,chan)  
#define QDMA_INTFLAG_CLR(chan)   RESET_BIT(CIPR,chan)


#endif /* _QDMA_H*/