//==================================================================
//  HAL_STRUCT information generated by 13700CFG.EXE (Build 1)
//  Copyright (c) 2003 Epson Research and Development, Inc.
//  All rights reserved.
//
//  DISPLAYS      WxHxBPP     FREQ    ADDITIONAL                                 
//  ------------- ----------- ------- -------------------------------------------
// 
//  DIMENSIONS    WxHxBPP @ STRIDE   START   SADDR                    ADDITIONAL 
//  ------------- ------------------ ------- ------------------------ -----------
// 
//  CLOCKS        FREQ        SOURCE                                             
//  ------------- ----------- ---------------------------------------------------
//  SYSCLK        6.000 MHz   CLKI
//  PCLK          1.500 MHz   sysclk/0
//
//  This file INSTANTIATES the HalInfo structure, and should
//  only be included, one time, by the mini-HAL.
//==================================================================

#include "hal_private.h"

#ifndef HAL_STRUCT_NAME
#define HAL_STRUCT_NAME HalInfo
#endif

HAL_STRUCT HAL_STRUCT_NAME =
{
    HALCHIPID" HAL EXE",    // HAL ID string
    "\x00",                 // Configuration description
    HALCHIPID,              // Chip ID

    sizeof(HAL_STRUCT),     // Sizeof this structure
    0xE361,                 // CRC of the rest of structure
    0x1234,                 // Endian detect (LE=0x1234)
    70L,                    // Desired frame rate (in Hz)

    6000000L,               // Embedded OSC frequency (in Hz)
    6000000L,               // CLKI frequency (in Hz)
    6000000L,               // PCLK frequency (in Hz)

    640,                    // in pixel
    200,                    // in line
    1,                      // Gray scale Bpp
    0,                      // Padding

    0x00000000,             // Physical base memory address
    0x00008000,             // Register offset form base address
    0x00000000,             // Memory offset form base address

    32768L,                 // Required VRAM (in bytes)
    0,                      // Hal Information flags

    {                       // S1D13700 init registers
        { REG0000_SYSTEMSET_P1,                 0x30 },
        { REG0001_SYSTEMSET_P2,                 0x87 },
        { REG0002_SYSTEMSET_P3,                 0x07 },
        { REG0003_SYSTEMSET_P4,                 0x4F },
        { REG0004_SYSTEMSET_P5,                 0x53 },
        { REG0005_SYSTEMSET_P6,                 0xC7 },
        { REG0006_SYSTEMSET_P7,                 0x50 },
        { REG0007_SYSTEMSET_P8,                 0x00 },
        { REG0008_SLEEPIN,                      0x00 },
        { REG0009_DISPONOFF,                    0x01 },
        { REG000A_DISPONOFF_P1,                 0x05 },
        { REG000B_SCROLL_P1,                    0x00 },
        { REG000C_SCROLL_P2,                    0x00 },
        { REG000D_SCROLL_P3,                    0xc7 },
        { REG000E_SCROLL_P4,                    0x80 },
        { REG000F_SCROLL_P5,                    0x1f },
        { REG0010_SCROLL_P6,                    0x27 },
        { REG0011_SCROLL_P7,                    0x20 },
        { REG0012_SCROLL_P8,                    0x30 },
        { REG0013_SCROLL_P9,                    0x24 },
        { REG0014_SCROLL_P10,                   0x60 },
        { REG0015_CSRFORM_P1,                   0x07 },
        { REG0016_CSRFORM_P2,                   0x87 },
        { REG0017_CSRDIR_P1,                    0x00 },
        { REG0018_OVLAY_P1,                     0x00 },
        { REG0019_CGRAMADDR_P1,                 0x00 },
        { REG001A_CGRAMADDR_P2,                 0x70 },
        { REG001B_HDOTSCR_P1,                   0x00 },
        { REG001C_CSRW_P1,                      0x00 },
        { REG001D_CSRW_P2,                      0x00 },
        { REG001E_CSRR_P1,                      0x00 },
        { REG001F_CSRR_P2,                      0x00 },
        { REG0020_GRAYSCALE_P1,                 0x00 },
        { REGFLAG_ENDOFTABLE,                   0x0000 }
    }
};