?? topmiaobiao.vhd
字號:
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY TopMiaobiao ISPORT(CLK,EN,RESET :IN STD_LOGIC; DisplaySEC01L:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); DisplaySEC01R:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); DisplaySECL :OUT STD_LOGIC_VECTOR(6 DOWNTO 0); DisplaySECR :OUT STD_LOGIC_VECTOR(6 DOWNTO 0); DisplayMINL :OUT STD_LOGIC_VECTOR(6 DOWNTO 0); DisplayMINR :OUT STD_LOGIC_VECTOR(6 DOWNTO 0) );END ENTITY TopMiaobiao;ARCHITECTURE ART OF TopMiaobiao IS COMPONENT miaobiao IS PORT(CLK,EN,RESET :IN STD_LOGIC; SEC01L,SEC01R :OUT INTEGER RANGE 0 TO 9; SECL, SECR :OUT INTEGER RANGE 0 TO 9; MINL ,MINR :OUT INTEGER RANGE 0 TO 9 ); END COMPONENT miaobiao; COMPONENT Display IS PORT(CLK :IN STD_LOGIC; DATA :IN INTEGER RANGE 0 TO 9; Display:OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ); END COMPONENT Display; SIGNAL SEC01L,SEC01R:INTEGER RANGE 0 TO 9; SIGNAL SECL,SECR :INTEGER RANGE 0 TO 9; SIGNAL MINL,MINR :INTEGER RANGE 0 TO 9; BEGIN MiaoBContr:miaobiao PORT MAP(CLK=>CLK,EN=>EN,RESET=>RESET, SEC01L=>SEC01L,SEC01R=>SEC01R, SECL=>SECL, SECR=>SECR, MINL=>MINL ,MINR=>MINR); DisSEC01L:Display PORT MAP(CLK=>CLK,DATA=>SEC01L,Display=>DisplaySEC01L); DisSEC01R:Display PORT MAP(CLK=>CLK,DATA=>SEC01R,Display=>DisplaySEC01R); DisSECL :Display PORT MAP(CLK=>CLK,DATA=>SECL, Display=>DisplaySECL); DisSECR :Display PORT MAP(CLK=>CLK,DATA=>SECR, Display=>DisplaySECR); DisMINL :Display PORT MAP(CLK=>CLK,DATA=>MINL, Display=>DisplayMINL); DisMINR :Display PORT MAP(CLK=>CLK,DATA=>MINR, Display=>DisplayMINR);END ARCHITECTURE ART;
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