#define 	AT91C_US_USMODE_ISO7816_0            0x4 /**< (USART) ISO7816 protocol: T = 0 */
#define 	AT91C_US_USMODE_ISO7816_1            0x6 /**< (USART) ISO7816 protocol: T = 1 */
#define 	AT91C_US_USMODE_IRDA                 0x8 /**< (USART) IrDA */
#define 	AT91C_US_USMODE_SWHSH                0xC /**< (USART) Software Handshaking */
#define AT91C_US_CLKS         (0x3 << 4 ) /**< (USART) Clock Selection (Baud Rate generator Input Clock */
#define 	AT91C_US_CLKS_CLOCK                (0x0 <<  4) /**< (USART) Clock */
#define 	AT91C_US_CLKS_FDIV1                (0x1 <<  4) /**< (USART) fdiv1 */
#define 	AT91C_US_CLKS_SLOW                 (0x2 <<  4) /**< (USART) slow_clock (ARM) */
#define 	AT91C_US_CLKS_EXT                  (0x3 <<  4) /**< (USART) External (SCK) */
#define AT91C_US_CHRL         (0x3 << 6 ) /**< (USART) Clock Selection (Baud Rate generator Input Clock */
#define 	AT91C_US_CHRL_5_BITS               (0x0 <<  6) /**< (USART) Character Length: 5 bits */
#define 	AT91C_US_CHRL_6_BITS               (0x1 <<  6) /**< (USART) Character Length: 6 bits */
#define 	AT91C_US_CHRL_7_BITS               (0x2 <<  6) /**< (USART) Character Length: 7 bits */
#define 	AT91C_US_CHRL_8_BITS               (0x3 <<  6) /**< (USART) Character Length: 8 bits */
#define AT91C_US_SYNC         (0x1 << 8 ) /**< (USART) Synchronous Mode Select */
#define AT91C_US_PAR          (0x7 << 9 ) /**< (USART) Parity type */
#define 	AT91C_US_PAR_EVEN                 (0x0 <<  9) /**< (USART) Even Parity */
#define 	AT91C_US_PAR_ODD                  (0x1 <<  9) /**< (USART) Odd Parity */
#define 	AT91C_US_PAR_SPACE                (0x2 <<  9) /**< (USART) Parity forced to 0 (Space) */
#define 	AT91C_US_PAR_MARK                 (0x3 <<  9) /**< (USART) Parity forced to 1 (Mark) */
#define 	AT91C_US_PAR_NONE                 (0x4 <<  9) /**< (USART) No Parity */
#define 	AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) /**< (USART) Multi-drop mode */
#define AT91C_US_NBSTOP       (0x3 << 12) /**< (USART) Number of Stop bits */
#define 	AT91C_US_NBSTOP_1_BIT                (0x0 << 12) /**< (USART) 1 stop bit */
#define 	AT91C_US_NBSTOP_15_BIT               (0x1 << 12) /**< (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */
#define 	AT91C_US_NBSTOP_2_BIT                (0x2 << 12) /**< (USART) 2 stop bits */
#define AT91C_US_CHMODE       (0x3 << 14) /**< (USART) Channel Mode */
#define 	AT91C_US_CHMODE_NORMAL               (0x0 << 14) /**< (USART) Normal Mode: The USART channel operates as an RX/TX USART. */
#define 	AT91C_US_CHMODE_AUTO                 (0x1 << 14) /**< (USART) Automatic Echo: Receiver Data Input is connected to the TXD pin. */
#define 	AT91C_US_CHMODE_LOCAL                (0x2 << 14) /**< (USART) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */
#define 	AT91C_US_CHMODE_REMOTE               (0x3 << 14) /**< (USART) Remote Loopback: RXD pin is internally connected to TXD pin. */
#define AT91C_US_MSBF         (0x1 << 16) /**< (USART) Bit Order */
#define AT91C_US_MODE9        (0x1 << 17) /**< (USART) 9-bit Character length */
#define AT91C_US_CKLO         (0x1 << 18) /**< (USART) Clock Output Select */
#define AT91C_US_OVER         (0x1 << 19) /**< (USART) Over Sampling Mode */
#define AT91C_US_INACK        (0x1 << 20) /**< (USART) Inhibit Non Acknowledge */
#define AT91C_US_DSNACK       (0x1 << 21) /**< (USART) Disable Successive NACK */
#define AT91C_US_MAX_ITER     (0x1 << 24) /**< (USART) Number of Repetitions */
#define AT91C_US_FILTER       (0x1 << 28) /**< (USART) Receive Line Filter */
/* --- Register US_IER */
#define AT91C_US_RXRDY        (0x1 << 0 ) /**< (USART) RXRDY Interrupt */
#define AT91C_US_TXRDY        (0x1 << 1 ) /**< (USART) TXRDY Interrupt */
#define AT91C_US_RXBRK        (0x1 << 2 ) /**< (USART) Break Received/End of Break */
#define AT91C_US_ENDRX        (0x1 << 3 ) /**< (USART) End of Receive Transfer Interrupt */
#define AT91C_US_ENDTX        (0x1 << 4 ) /**< (USART) End of Transmit Interrupt */
#define AT91C_US_OVRE         (0x1 << 5 ) /**< (USART) Overrun Interrupt */
#define AT91C_US_FRAME        (0x1 << 6 ) /**< (USART) Framing Error Interrupt */
#define AT91C_US_PARE         (0x1 << 7 ) /**< (USART) Parity Error Interrupt */
#define AT91C_US_TIMEOUT      (0x1 << 8 ) /**< (USART) Receiver Time-out */
#define AT91C_US_TXEMPTY      (0x1 << 9 ) /**< (USART) TXEMPTY Interrupt */
#define AT91C_US_ITERATION    (0x1 << 10) /**< (USART) Max number of Repetitions Reached */
#define AT91C_US_TXBUFE       (0x1 << 11) /**< (USART) TXBUFE Interrupt */
#define AT91C_US_RXBUFF       (0x1 << 12) /**< (USART) RXBUFF Interrupt */
#define AT91C_US_NACK         (0x1 << 13) /**< (USART) Non Acknowledge */
#define AT91C_US_RIIC         (0x1 << 16) /**< (USART) Ring INdicator Input Change Flag */
#define AT91C_US_DSRIC        (0x1 << 17) /**< (USART) Data Set Ready Input Change Flag */
#define AT91C_US_DCDIC        (0x1 << 18) /**< (USART) Data Carrier Flag */
#define AT91C_US_CTSIC        (0x1 << 19) /**< (USART) Clear To Send Input Change Flag */
/* --- Register US_IDR */
#define AT91C_US_RXRDY        (0x1 << 0 ) /**< (USART) RXRDY Interrupt */
#define AT91C_US_TXRDY        (0x1 << 1 ) /**< (USART) TXRDY Interrupt */
#define AT91C_US_RXBRK        (0x1 << 2 ) /**< (USART) Break Received/End of Break */
#define AT91C_US_ENDRX        (0x1 << 3 ) /**< (USART) End of Receive Transfer Interrupt */
#define AT91C_US_ENDTX        (0x1 << 4 ) /**< (USART) End of Transmit Interrupt */
#define AT91C_US_OVRE         (0x1 << 5 ) /**< (USART) Overrun Interrupt */
#define AT91C_US_FRAME        (0x1 << 6 ) /**< (USART) Framing Error Interrupt */
#define AT91C_US_PARE         (0x1 << 7 ) /**< (USART) Parity Error Interrupt */
#define AT91C_US_TIMEOUT      (0x1 << 8 ) /**< (USART) Receiver Time-out */
#define AT91C_US_TXEMPTY      (0x1 << 9 ) /**< (USART) TXEMPTY Interrupt */
#define AT91C_US_ITERATION    (0x1 << 10) /**< (USART) Max number of Repetitions Reached */
#define AT91C_US_TXBUFE       (0x1 << 11) /**< (USART) TXBUFE Interrupt */
#define AT91C_US_RXBUFF       (0x1 << 12) /**< (USART) RXBUFF Interrupt */
#define AT91C_US_NACK         (0x1 << 13) /**< (USART) Non Acknowledge */
#define AT91C_US_RIIC         (0x1 << 16) /**< (USART) Ring INdicator Input Change Flag */
#define AT91C_US_DSRIC        (0x1 << 17) /**< (USART) Data Set Ready Input Change Flag */
#define AT91C_US_DCDIC        (0x1 << 18) /**< (USART) Data Carrier Flag */
#define AT91C_US_CTSIC        (0x1 << 19) /**< (USART) Clear To Send Input Change Flag */
/* --- Register US_IMR */
#define AT91C_US_RXRDY        (0x1 << 0 ) /**< (USART) RXRDY Interrupt */
#define AT91C_US_TXRDY        (0x1 << 1 ) /**< (USART) TXRDY Interrupt */
#define AT91C_US_RXBRK        (0x1 << 2 ) /**< (USART) Break Received/End of Break */
#define AT91C_US_ENDRX        (0x1 << 3 ) /**< (USART) End of Receive Transfer Interrupt */
#define AT91C_US_ENDTX        (0x1 << 4 ) /**< (USART) End of Transmit Interrupt */
#define AT91C_US_OVRE         (0x1 << 5 ) /**< (USART) Overrun Interrupt */
#define AT91C_US_FRAME        (0x1 << 6 ) /**< (USART) Framing Error Interrupt */
#define AT91C_US_PARE         (0x1 << 7 ) /**< (USART) Parity Error Interrupt */
#define AT91C_US_TIMEOUT      (0x1 << 8 ) /**< (USART) Receiver Time-out */
#define AT91C_US_TXEMPTY      (0x1 << 9 ) /**< (USART) TXEMPTY Interrupt */
#define AT91C_US_ITERATION    (0x1 << 10) /**< (USART) Max number of Repetitions Reached */
#define AT91C_US_TXBUFE       (0x1 << 11) /**< (USART) TXBUFE Interrupt */
#define AT91C_US_RXBUFF       (0x1 << 12) /**< (USART) RXBUFF Interrupt */
#define AT91C_US_NACK         (0x1 << 13) /**< (USART) Non Acknowledge */
#define AT91C_US_RIIC         (0x1 << 16) /**< (USART) Ring INdicator Input Change Flag */
#define AT91C_US_DSRIC        (0x1 << 17) /**< (USART) Data Set Ready Input Change Flag */
#define AT91C_US_DCDIC        (0x1 << 18) /**< (USART) Data Carrier Flag */
#define AT91C_US_CTSIC        (0x1 << 19) /**< (USART) Clear To Send Input Change Flag */
/* --- Register US_CSR */
#define AT91C_US_RXRDY        (0x1 << 0 ) /**< (USART) RXRDY Interrupt */
#define AT91C_US_TXRDY        (0x1 << 1 ) /**< (USART) TXRDY Interrupt */
#define AT91C_US_RXBRK        (0x1 << 2 ) /**< (USART) Break Received/End of Break */
#define AT91C_US_ENDRX        (0x1 << 3 ) /**< (USART) End of Receive Transfer Interrupt */
#define AT91C_US_ENDTX        (0x1 << 4 ) /**< (USART) End of Transmit Interrupt */
#define AT91C_US_OVRE         (0x1 << 5 ) /**< (USART) Overrun Interrupt */
#define AT91C_US_FRAME        (0x1 << 6 ) /**< (USART) Framing Error Interrupt */
#define AT91C_US_PARE         (0x1 << 7 ) /**< (USART) Parity Error Interrupt */
#define AT91C_US_TIMEOUT      (0x1 << 8 ) /**< (USART) Receiver Time-out */
#define AT91C_US_TXEMPTY      (0x1 << 9 ) /**< (USART) TXEMPTY Interrupt */
#define AT91C_US_ITERATION    (0x1 << 10) /**< (USART) Max number of Repetitions Reached */
#define AT91C_US_TXBUFE       (0x1 << 11) /**< (USART) TXBUFE Interrupt */
#define AT91C_US_RXBUFF       (0x1 << 12) /**< (USART) RXBUFF Interrupt */
#define AT91C_US_NACK         (0x1 << 13) /**< (USART) Non Acknowledge */
#define AT91C_US_RIIC         (0x1 << 16) /**< (USART) Ring INdicator Input Change Flag */
#define AT91C_US_DSRIC        (0x1 << 17) /**< (USART) Data Set Ready Input Change Flag */
#define AT91C_US_DCDIC        (0x1 << 18) /**< (USART) Data Carrier Flag */
#define AT91C_US_CTSIC        (0x1 << 19) /**< (USART) Clear To Send Input Change Flag */
#define AT91C_US_RI           (0x1 << 20) /**< (USART) Image of RI Input */
#define AT91C_US_DSR          (0x1 << 21) /**< (USART) Image of DSR Input */
#define AT91C_US_DCD          (0x1 << 22) /**< (USART) Image of DCD Input */
#define AT91C_US_CTS          (0x1 << 23) /**< (USART) Image of CTS Input */

#endif /* __AT91SAM7X256_USART_H */