?? switcher_bus.vhd
字號:
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity switch_bus is
generic(BUS_WIDTH:integer:=8);
port(din1:in std_logic_vector(BUS_WIDTH-1 downto 0);
din2:in std_logic_vector(BUS_WIDTH-1 downto 0);
sel:in std_logic;
dout:out std_logic_vector(BUS_WIDTH-1 downto 0));
end switch_bus;
architecture switch_bus of switch_bus is
begin
with sel select
dout<=din1 when '0',
din2 when others;
end switch_bus;
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