--
library IEEE;
use IEEE.STD_LOGIC_1164.all;

--
entity shift_register is
	--
	generic(TOTAL_BIT:integer:=10);
	--
	port(clk:in std_logic;
		 reset_n:in std_logic;
		 din:in std_logic;
		 regs:out std_logic_vector(TOTAL_BIT-1 downto 0);
		 dout:out std_logic);
end shift_register;

architecture shift_register of shift_register is
signal shift_regs:std_logic_vector(TOTAL_BIT-1 downto 0):=(others=>'1');
begin
	--
	regs<=shift_regs;
	main:process(clk,reset_n)
	begin
		if reset_n='0' then 
			dout<='1';
		elsif rising_edge(clk) then 
			dout<=shift_regs(TOTAL_BIT-1);
			--
			shift_regs(TOTAL_BIT-1 downto 1)<=shift_regs(TOTAL_BIT-2 downto 0);
			--
			shift_regs(0)<=din;
		end if;
	end process;
end shift_register;