--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use WORK.UART_PACKAGE.ALL;
--
entity detector is
port(clk:in std_logic;
	 reset_n:in std_logic;
	 RxD:in std_logic;
	 new_data:out std_logic);
end detector;

--
architecture detector of detector is
signal state:dt_state;
begin
	--
	main:process(reset_n,clk)
	begin
		--
		if reset_n='0' then 
			state<=dt_unlock;
			new_data<='0';
		elsif rising_edge(clk) then 
			--
			if state=dt_unlock and RxD='0' then 
				new_data<='1';
				state<=dt_lock;
			else 
				new_data<='0';
			end if ;
		end if;
		
	end process;
end detector;