?? sfr62.h
字號(hào):
Protect register
------------------------------------------------------*/
union byte_def prcr_addr;
#define prcr prcr_addr.byte
#define prc0 prcr_addr.bit.b0 /* Enables writing to system clock control registers 0 and 1 */
#define prc1 prcr_addr.bit.b1 /* Enables writing to processor mode registers 0 and 1 */
#define prc2 prcr_addr.bit.b2 /* Enables writing to port P9 direction register and SI/Oi control register(i=3,4) */
/*------------------------------------------------------
Data bank register
------------------------------------------------------*/
union byte_def dbr_addr;
#define dbr dbr_addr.byte
#define ofs dbr_addr.bit.b2 /* Offset bit */
#define bsr0 dbr_addr.bit.b3 /* Bank select bit 0 */
#define bsr1 dbr_addr.bit.b4 /* Bank select bit 1 */
#define bsr2 dbr_addr.bit.b5 /* Bank select bit 2 */
/*------------------------------------------------------
Watchdog timer start register
------------------------------------------------------*/
union byte_def wdts_addr;
#define wdts wdts_addr.byte
/*------------------------------------------------------
CRC input register
------------------------------------------------------*/
union byte_def crcin_addr;
#define crcin crcin_addr.byte
/*------------------------------------------------------
Watchdog timer control register
------------------------------------------------------*/
union byte_def wdc_addr;
#define wdc wdc_addr.byte
/* #define wdc5 wdc_addr.bit.b5 */ /* Remove 2000.6.21 */
/* #define wdc6 wdc_addr.bit.b6 */ /* Remove 2000.6.21 */
#define wdc7 wdc_addr.bit.b7 /* Prescaler select bit */
/*------------------------------------------------------
Count start flag
------------------------------------------------------*/
union byte_def tabsr_addr;
#define tabsr tabsr_addr.byte
#define ta0s tabsr_addr.bit.b0 /* Timer A0 count start flag */
#define ta1s tabsr_addr.bit.b1 /* Timer A1 count start flag */
#define ta2s tabsr_addr.bit.b2 /* Timer A2 count start flag */
#define ta3s tabsr_addr.bit.b3 /* Timer A3 count start flag */
#define ta4s tabsr_addr.bit.b4 /* Timer A4 count start flag */
#define tb0s tabsr_addr.bit.b5 /* Timer B0 count start flag */
#define tb1s tabsr_addr.bit.b6 /* Timer B1 count start flag */
#define tb2s tabsr_addr.bit.b7 /* Timer B2 count start flag */
/*------------------------------------------------------
Timer B3,4,5 Count start flag
------------------------------------------------------*/
union byte_def tbsr_addr;
#define tbsr tbsr_addr.byte
#define tb3s tbsr_addr.bit.b5 /* Timer B3 count start flag */
#define tb4s tbsr_addr.bit.b6 /* Timer B4 count start flag */
#define tb5s tbsr_addr.bit.b7 /* Timer B5 count start flag */
/*------------------------------------------------------
Three-phase PWM control regester 0
------------------------------------------------------*/
union byte_def invc0_addr;
#define invc0 invc0_addr.byte
#define inv00 invc0_addr.bit.b0 /* Effective interrupt output polarity select bit */
#define inv01 invc0_addr.bit.b1 /* Effective interrupt output specification bit */
#define inv02 invc0_addr.bit.b2 /* Mode select bit */
#define inv03 invc0_addr.bit.b3 /* Output control bit */
#define inv04 invc0_addr.bit.b4 /* Positive and negative phases concurrent L output disable function enable bit */
#define inv05 invc0_addr.bit.b5 /* Positive and negative phases concurrent L output detect flag */
#define inv06 invc0_addr.bit.b6 /* Modulation mode select bit */
#define inv07 invc0_addr.bit.b7 /* Software trigger bit */
/*------------------------------------------------------
Three-phase PWM control regester 1
------------------------------------------------------*/
union byte_def invc1_addr;
#define invc1 invc1_addr.byte
#define inv10 invc1_addr.bit.b0 /* Timer Ai start trigger signal select bit */
#define inv11 invc1_addr.bit.b1 /* Timer A1-1,A2-1,A4-1 control bit */
#define inv12 invc1_addr.bit.b2 /* Short circuit timer count source select bit */
/* #define inv14 invc1_addr.bit.b4 /* Reserved bit ; Remove 2000.6.21 */
/*------------------------------------------------------
Three-phase output buffer register 0
------------------------------------------------------*/
union byte_def idb0_addr;
#define idb0 idb0_addr.byte
#define du0 idb0_addr.bit.b0 /* U phase output buffer 0 */
#define dub0 idb0_addr.bit.b1 /* U~ phase output buffer 0 */
#define dv0 idb0_addr.bit.b2 /* V phase output buffer 0 */
#define dvb0 idb0_addr.bit.b3 /* V~ phase output buffer 0 */
#define dw0 idb0_addr.bit.b4 /* W phase output buffer 0 */
#define dwb0 idb0_addr.bit.b5 /* W~ phase output buffer 0 */
/*------------------------------------------------------
Three-phase output buffer register 1
------------------------------------------------------*/
union byte_def idb1_addr;
#define idb1 idb1_addr.byte
#define du1 idb1_addr.bit.b0 /* U phase output buffer 1 */
#define dub1 idb1_addr.bit.b1 /* U~ phase output buffer 1 */
#define dv1 idb1_addr.bit.b2 /* V phase output buffer 1 */
#define dvb1 idb1_addr.bit.b3 /* V~ phase output buffer 1 */
#define dw1 idb1_addr.bit.b4 /* W phase output buffer 1 */
#define dwb1 idb1_addr.bit.b5 /* W~ phase output buffer 1 */
/*------------------------------------------------------
Dead time timer ; Use "MOV" instruction when writing to this register.
------------------------------------------------------*/
union byte_def dtt_addr;
#define dtt dtt_addr.byte
/*------------------------------------------------------------------
Timer B2 interrupt occurrences frequency set counter
; Use "MOV" instruction when writing to this register.
-------------------------------------------------------------------*/
union byte_def ictb2_addr;
#define ictb2 ictb2_addr.byte
/*------------------------------------------------------
One-shot start flag
------------------------------------------------------*/
union byte_def onsf_addr;
#define onsf onsf_addr.byte
#define ta0os onsf_addr.bit.b0 /* Timer A0 one-shot start flag */
#define ta1os onsf_addr.bit.b1 /* Timer A1 one-shot start flag */
#define ta2os onsf_addr.bit.b2 /* Timer A2 one-shot start flag */
#define ta3os onsf_addr.bit.b3 /* Timer A3 one-shot start flag */
#define ta4os onsf_addr.bit.b4 /* Timer A4 one-shot start flag */
#define ta0tgl onsf_addr.bit.b6 /* Timer A0 event/trigger select bit */
#define ta0tgh onsf_addr.bit.b7 /* Timer A0 event/trigger select bit */
/*------------------------------------------------------
Clock prescaler reset flag
------------------------------------------------------*/
union byte_def cpsrf_addr;
#define cpsrf cpsrf_addr.byte
#define cpsr cpsrf_addr.bit.b7 /* Clock prescaler reset flag */
/*------------------------------------------------------
Trigger select register
------------------------------------------------------*/
union byte_def trgsr_addr;
#define trgsr trgsr_addr.byte
#define ta1tgl trgsr_addr.bit.b0 /* Timer A1 event/trigger select bit */
#define ta1tgh trgsr_addr.bit.b1 /* Timer A1 event/trigger select bit */
#define ta2tgl trgsr_addr.bit.b2 /* Timer A2 event/trigger select bit */
#define ta2tgh trgsr_addr.bit.b3 /* Timer A2 event/trigger select bit */
#define ta3tgl trgsr_addr.bit.b4 /* Timer A3 event/trigger select bit */
#define ta3tgh trgsr_addr.bit.b5 /* Timer A3 event/trigger select bit */
#define ta4tgl trgsr_addr.bit.b6 /* Timer A4 event/trigger select bit */
#define ta4tgh trgsr_addr.bit.b7 /* Timer A4 event/trigger select bit */
/*------------------------------------------------------
Up/down flag
------------------------------------------------------*/
union byte_def udf_addr; /* modify 2000.6.21 */
#define udf udf_addr.byte
#define ta0ud udf_addr.bit.b0 /* Timer A0 up/down flag ; */
#define ta1ud udf_addr.bit.b1 /* Timer A1 up/down flag ; */
#define ta2ud udf_addr.bit.b2 /* Timer A2 up/down flag ; */
#define ta3ud udf_addr.bit.b3 /* Timer A3 up/down flag ; */
#define ta4ud udf_addr.bit.b4 /* Timer A4 up/down flag ; */
#define ta2p udf_addr.bit.b5 /* Timer A2 two-phase pulse signal processing select bit ;*/
#define ta3p udf_addr.bit.b6 /* Timer A3 two-phase pulse signal processing select bit ;*/
#define ta4p udf_addr.bit.b7 /* Timer A4 two-phase pulse signal processing select bit ;*/
/*------------------------------------------------------
UART transmit/receive control register 2
------------------------------------------------------*/
union byte_def ucon_addr;
#define ucon ucon_addr.byte
#define u0irs ucon_addr.bit.b0 /* UART0 transmit interrupt cause select bit */
#define u1irs ucon_addr.bit.b1 /* UART1 transmit interrupt cause select bit */
#define u0rrm ucon_addr.bit.b2 /* UART0 continuous receive mode enable bit */
#define u1rrm ucon_addr.bit.b3 /* UART1 continuous receive mode enable bit */
#define clkmd0 ucon_addr.bit.b4 /* CLK/CLKS select bit 0 */
#define clkmd1 ucon_addr.bit.b5 /* CLK/CLKS select bit 1 */
#define rcsp ucon_addr.bit.b6 /* Separate CTS~/RTS~ bit */
/*------------------------------------------------------
UART2 transmit/receive control register 1
------------------------------------------------------*/
union byte_def u2c1_addr;
#define u2c1 u2c1_addr.byte
#define te_u2c1 u2c1_addr.bit.b0 /* Transmit enable bit */
#define ti_u2c1 u2c1_addr.bit.b1 /* Transmit buffer empty flag */
#define re_u2c1 u2c1_addr.bit.b2 /* Receive enable bit */
#define ri_u2c1 u2c1_addr.bit.b3 /* Receive complete flag */
#define u2irs u2c1_addr.bit.b4 /* UART2 transmit interrupt cause select bit */
#define u2rrm u2c1_addr.bit.b5 /* UART2 continuous receive mode enable bit */
#define u2lch u2c1_addr.bit.b6 /* Data logic select bit */
#define u2ere u2c1_addr.bit.b7 /* Error signal output enable bit */
/*------------------------------------------------------
UART2 special mode register 3
------------------------------------------------------*/
/* union byte_def u2smr3_addr; */ /* Remove 2000.7.27 */
/* #define u2smr3 u2smr3_addr.byte */ /* Remove 2000.7.27 */
/* #define dl0 u2smr3_addr.bit.b5 /* SDA digital delay setup bit */ /* Remove 2000.7.27 */
/* #define dl1 u2smr3_addr.bit.b6 /* SDA digital delay setup bit */ /* Remove 2000.7.27 */
/* #define dl2 u2smr3_addr.bit.b7 /* SDA digital delay setup bit */ /* Remove 2000.7.27 */
/*------------------------------------------------------
UART2 special mode register 2
------------------------------------------------------*/
union byte_def u2smr2_addr;
#define u2smr2 u2smr2_addr.byte
#define iicm2 u2smr2_addr.bit.b0 /* IIC mode selection bit 2 */
#define csc u2smr2_addr.bit.b1 /* Clock-synchronous bit */
#define swc u2smr2_addr.bit.b2 /* SCL wait output bit */
#define als u2smr2_addr.bit.b3 /* SDA output stop bit */
#define stac u2smr2_addr.bit.b4 /* UART2 initialization bit */
#define swc2 u2smr2_addr.bit.b5 /* SCL wait output bit 2 */
#define sdhi u2smr2_addr.bit.b6 /* SDA output disable bit */
#define shtc u2smr2_addr.bit.b7 /* Start/stop condition control bit */
/*------------------------------------------------------
UART2 special mode register
------------------------------------------------------*/
union byte_def u2smr_addr;
#define u2smr u2smr_addr.byte
#define iicm u2smr_addr.bit.b0 /* IIC mode selection bit */
#define abc u2smr_addr.bit.b1 /* Arbitration lost detecting flag control bit */
#define bbs u2smr_addr.bit.b2 /* Bus busy flag */
#define lsyn u2smr_addr.bit.b3 /* SCLL sync output enable bit */
#define abscs u2smr_addr.bit.b4 /* Bus collision detect sampling clock select bit */
#define acse u2smr_addr.bit.b5 /* Auto clear function select bit of transmit enable bit */
#define sss u2smr_addr.bit.b6 /* Transmit start condition select bit */
/* #define sdds u2smr_addr.bit.b7 /* SDA digital delay select bit (62A) /* /* Remove 2000.7.27 */
/*------------------------------------------------------
A-D control register 0
------------------------------------------------------*/
union byte_def adcon0_addr;
#define adcon0 adcon0_addr.byte
#define ch0 adcon0_addr.bit.b0 /* Analog input pin select bit */
#define ch1 adcon0_addr.bit.b1 /* Analog input pin select bit */
#define ch2 adcon0_addr.bit.b2 /* Analog input pin select bit */
#define md0 adcon0_addr.bit.b3 /* A-D operation mode select bit 0 */
#define md1 adcon0_addr.bit.b4 /* A-D operation mode select bit 0 */
#define trg adcon0_addr.bit.b5 /* Trigger select bit */
#define adst adcon0_addr.bit.b6 /* A-D conversion start flag */
#define cks0 adcon0_addr.bit.b7 /* Frequency select bit 0 */
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