if ( (hostdata->state != PXA_MMC_FSM_END_CMD) && (hostdata->state != PXA_MMC_FSM_END_BUFFER) ) {            goto error;	}		if ( cnt > hostdata->iobuf.bufsz )		cnt = hostdata->iobuf.bufsz;	if ( (ret = pxa_mmc_iobuf_init( ctrlr, cnt )) )		goto error; 	pxa_mmc_set_state( ctrlr, PXA_MMC_FSM_BUFFER_IN_TRANSIT );#ifndef PIO	if ( pxa_mmc_init_completion( ctrlr, ~MMC_I_MASK_ALL ) ) /* FIXME */		goto error;		if ( (desc = hostdata->iobuf.buf.last_read_desc) ) {		desc->ddadr &= ~DDADR_STOP;		desc->dcmd &= ~(DCMD_ENDIRQEN|DCMD_LENGTH);		desc->dcmd |= (1<<5);	}/* 1) setup descriptors for DMA transfer from the device */	ndesc = (cnt>>5) - 1; /* FIXME: partial read */	desc = &hostdata->iobuf.buf.read_desc[ndesc];	hostdata->iobuf.buf.last_read_desc = desc;		/* TODO: partial read */	desc->ddadr |= DDADR_STOP;	desc->dcmd |= DCMD_ENDIRQEN;/* 2) start DMA channel */	DDADR( chan ) = hostdata->iobuf.buf.read_desc_phys_addr;	DCSR( chan ) |= DCSR_RUN;     #else	if ( pxa_mmc_init_completion( ctrlr, MMC_I_MASK_RXFIFO_RD_REQ ) )		goto error;#endif     	if ( pxa_mmc_wait_for_completion( ctrlr, ~0UL ) )		goto error;	if ( pxa_mmc_check_state( ctrlr, PXA_MMC_FSM_END_BUFFER ) )		goto error;        	if ( !(hostdata->mmc_stat & MMC_STAT_ERRORS) ) /* FIXME */  		ret = cnt;error:	return ret;}ssize_t pxa_mmc_write_buffer( mmc_controller_t ctrlr, ssize_t cnt ){	ssize_t ret = -EIO;	pxa_mmc_hostdata_t hostdata = (pxa_mmc_hostdata_t)ctrlr->host_data;#ifndef PIO	register int ndesc;	int chan = hostdata->iobuf.buf.chan;	pxa_dma_desc *desc;#endif		if ( (hostdata->state != PXA_MMC_FSM_END_CMD) 	    && (hostdata->state != PXA_MMC_FSM_END_BUFFER) ) {		MMC_DEBUG( MMC_DEBUG_LEVEL3, "unexpected state (%s)\n",			PXA_MMC_STATE_LABEL( hostdata->state ) ); 		goto error;	}    	if ( cnt > hostdata->iobuf.bufsz )		cnt = hostdata->iobuf.bufsz;		if ( (ret = pxa_mmc_iobuf_init( ctrlr, cnt )) )		goto error;    	pxa_mmc_set_state( ctrlr, PXA_MMC_FSM_BUFFER_IN_TRANSIT );#ifndef PIO	if ( pxa_mmc_init_completion( ctrlr, ~MMC_I_MASK_ALL ) ) /* FIXME */		goto error;	if ( (desc = hostdata->iobuf.buf.last_write_desc) ) {		desc->ddadr &= ~DDADR_STOP;		desc->dcmd &= ~(DCMD_ENDIRQEN|DCMD_LENGTH);		desc->dcmd |= (1<<5);	}/* 1) setup descriptors for DMA transfer to the device */	ndesc = (cnt>>5) - 1; /* FIXME: partial write */	desc = &hostdata->iobuf.buf.write_desc[ndesc];	/* TODO: partial write */	hostdata->iobuf.buf.last_write_desc = desc;		desc->ddadr |= DDADR_STOP;	desc->dcmd |= DCMD_ENDIRQEN;/* 2) start DMA channel */	DDADR( chan ) = hostdata->iobuf.buf.write_desc_phys_addr;	DCSR( chan ) |= DCSR_RUN;#else       // printk("%s::%s\n", __FILE__, __FUNCTION__);	if ( pxa_mmc_init_completion( ctrlr, MMC_I_MASK_TXFIFO_WR_REQ ) )		goto error;#endif	if ( pxa_mmc_wait_for_completion( ctrlr, ~0UL ) )		goto error;    	if ( pxa_mmc_check_state( ctrlr, PXA_MMC_FSM_END_BUFFER ) )		goto error;	if ( !(hostdata->mmc_stat & MMC_STAT_ERRORS) ) /* FIXME */  		ret = cnt;error:	return ret;}/* TODO: ssize_t pxa_mmc_copy_from_buffer( ctrlr, mmc_buftype_t to, char *buf, ssize_t cnt )effects: copies at most cnt bytes from the controller I/O buffer to the user or kernel buffer         pointed by bufrequiers:modifies:returns: number of bytes actually transferred or negative error code if there were any errors */ ssize_t pxa_mmc_copy_from_buffer( mmc_controller_t ctrlr, mmc_buftype_t to, char *buf, ssize_t cnt ){	ssize_t ret = -EIO;	pxa_mmc_hostdata_t hostdata = (pxa_mmc_hostdata_t)ctrlr->host_data;#ifndef PIO/* TODO: check that DMA channel is not running */#endif	switch ( to ) {	case MMC_USER:		if ( copy_to_user( buf, hostdata->iobuf.iodata, cnt ) ) {			ret = -EFAULT;			goto error;		}		break;        case MMC_KERNEL:		memcpy( buf, hostdata->iobuf.iodata, cnt );		break;        default:		MMC_DEBUG( MMC_DEBUG_LEVEL3, "unknown buffer type\n" );		goto error;	}	ret = cnt;error:	return ret;}ssize_t pxa_mmc_copy_to_buffer( mmc_controller_t ctrlr, mmc_buftype_t to, char *buf, ssize_t cnt ){	ssize_t ret = -EIO;	pxa_mmc_hostdata_t hostdata = (pxa_mmc_hostdata_t)ctrlr->host_data;#ifndef PIO/* check that DMA channel is not running */#endif	switch ( to ) {	case MMC_USER:		if ( copy_from_user( hostdata->iobuf.iodata, buf, cnt ) ) {			ret = -EFAULT;			goto error;		}		break;	case MMC_KERNEL:		memcpy( hostdata->iobuf.iodata, buf, cnt );		break;	default:		MMC_DEBUG( MMC_DEBUG_LEVEL3, "unknown buffer type\n" );		goto error;	}	ret = cnt;error:	return ret;}/* This procedure sequentally passes the data from the user buffer to the card */static int pxa_mmc_stream_read( mmc_controller_t ctrlr, mmc_data_transfer_req_t transfer ){	int ret = -EIO;	pxa_mmc_hostdata_t hostdata = (pxa_mmc_hostdata_t)ctrlr->host_data;	u16 argh = 0UL, argl = 0UL;	ssize_t size = 0;       // printk(KERN_EMERG"%s::%s\n\n", __FILE__, __FUNCTION__);	while ( transfer->cnt > 0 ) {		size = (transfer->cnt < hostdata->iobuf.blksz) ?			transfer->cnt : hostdata->iobuf.blksz; 		/* 1. send CMD11 */		if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) )			goto error;		argh = transfer->addr >> 16;		argl = transfer->addr;		/* 2. setup controller registers to start stream data transfer */		MMC_CMD = CMD(11); /* READ_DAT_UNTIL_STOP */		MMC_ARGH = argh;		MMC_ARGL = argl;		MMC_NOB = 0xffff;		MMC_BLKLEN = size;		MMC_CMDAT = MMC_CMDAT_R1|MMC_CMDAT_READ|MMC_CMDAT_STREAM|MMC_CMDAT_DATA_EN;#ifndef PIO		MMC_CMDAT |= MMC_CMDAT_MMC_DMA_EN; #endif		/* 3. wait for cmd to complete */		MMC_DEBUG( MMC_DEBUG_LEVEL3, "CMD11(0x%04x%04x)\n", argh, argl );		if ( (ret = pxa_mmc_complete_cmd( ctrlr, MMC_R1, TRUE )) )			goto error;	    		/* 4. transfer the data to the caller supplied buffer */		if ( (ret = pxa_mmc_read_buffer( ctrlr, size )) < 0 )			goto error;		if ( (ret = pxa_mmc_copy_from_buffer( ctrlr, transfer->type, transfer->buf, ret )) < 0 )			goto error;        		pxa_mmc_set_state( ctrlr, PXA_MMC_FSM_END_IO );		if ( (ret = pxa_mmc_complete_io( ctrlr, transfer->cmd, transfer->mode )) )			goto error;	        		transfer->buf += ret;		transfer->addr += ret;		transfer->cnt -= ret;	}	ret = 0;    error:	return ret;}/* This procedure reads a data block from a card at a given kernel address */ static int pxa_mmc_read_block( mmc_controller_t ctrlr, mmc_data_transfer_req_t transfer ){	int ret = -ENODEV;	u16 argh = 0UL, argl = 0UL;      // printk(KERN_EMERG"%s::%s\n\n",__FILE__, __FUNCTION__);/* send CMD16 (SET_BLOCK_LEN) when requested block size is not the default * for the current card */  	if ( transfer->blksz != ctrlr->stack.selected->info.read_bl_len ) {		argh = transfer->blksz >> 16;		argl = transfer->blksz;		if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) ) 			goto error;    		MMC_CMD = CMD(16); /* SET_BLOCK_LEN */		MMC_ARGH = argh;		MMC_ARGL = argl;		MMC_CMDAT = MMC_CMDAT_R1;        		MMC_DEBUG( MMC_DEBUG_LEVEL3, 				"CMD16(0x%04x%04x)\n", argh, argl );		if ( (ret = pxa_mmc_complete_cmd( ctrlr, MMC_R1, FALSE )) )			goto error;   	}   /* CMD17 (READ_SINGLE_BLOCK) */	argh = transfer->addr >> 16;	argl = transfer->addr;	if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) )		goto error;		MMC_CMD = CMD(17); /* READ_SINGLE_BLOCK */	MMC_ARGH = argh;	MMC_ARGL = argl;	MMC_CMDAT = MMC_CMDAT_R1|MMC_CMDAT_READ|MMC_CMDAT_BLOCK|MMC_CMDAT_DATA_EN  ;	MMC_NOB = 1;	MMC_BLKLEN = transfer->blksz;        //printk(KERN_EMERG"MMC_BLKLEN IS 0x%08x\n", MMC_BLKLEN);#ifndef PIO        asdf	MMC_CMDAT |= MMC_CMDAT_MMC_DMA_EN; #endif    	MMC_DEBUG( MMC_DEBUG_LEVEL3, "CMD17(0x%04x%04x)\n", argh, argl );	if ( (ret = pxa_mmc_complete_cmd( ctrlr, MMC_R1, FALSE )) )		goto error;           // printk(KERN_EMERG"transfer the data \n "); /* transfer the data to the caller supplied buffer */	if ( (ret = pxa_mmc_read_buffer( ctrlr, transfer->blksz )) < 0 )    //transfer->blksz 		goto error;	if ( (ret = pxa_mmc_copy_from_buffer( ctrlr, transfer->type, transfer->buf, ret )) < 0 )		goto error;        	transfer->buf += ret;	transfer->cnt -= ret;	transfer->nob -= 1;    	pxa_mmc_set_state( ctrlr, PXA_MMC_FSM_END_IO );	if ( (ret = pxa_mmc_complete_io( ctrlr, transfer->cmd, transfer->mode )) )		goto error;    	ret = 0;    error:	return ret;}/* This procedure sequentally reads data blocks from * a card to the user buffer. Controller options and block size  * are already set by setup_card(). Data alignment and partial * data accessibility assumed to be checked by mmc_core */static int pxa_mmc_read_mblock( mmc_controller_t ctrlr, mmc_data_transfer_req_t transfer ){	int ret = -EIO;	u16 argh = 0UL, argl = 0UL;      //  printk(KERN_EMERG"%s::%s\n\n", __FILE__, __FUNCTION__);/* send CMD16 (SET_BLOCK_LEN) when requested block size is not the default * for the current card */  	if ( transfer->blksz != ctrlr->stack.selected->info.read_bl_len ) {		argh = transfer->blksz >> 16;		argl = transfer->blksz;		if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) )			goto error;    		MMC_CMD = CMD(16); /* SET_BLOCK_LEN */		MMC_ARGH = argh;		MMC_ARGL = argl;		MMC_CMDAT = MMC_CMDAT_R1;        		MMC_DEBUG( MMC_DEBUG_LEVEL3, "CMD16(0x%04x%04x)\n", argh, argl );		if ( (ret = pxa_mmc_complete_cmd( ctrlr, MMC_R1, FALSE )) )			goto error;	}    	argh = transfer->addr >> 16;	argl = transfer->addr;/* 1. stop bus clock */	if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) )		goto error;/* 2. setup controller registers to start multiple block transfer */	MMC_CMD = CMD(18); /* READ_MULTIPLE_BLOCK */	MMC_ARGH = argh;	MMC_ARGL = argl;	MMC_NOB = transfer->nob;	MMC_BLKLEN = transfer->blksz;	MMC_CMDAT = MMC_CMDAT_R1|MMC_CMDAT_READ|MMC_CMDAT_BLOCK|MMC_CMDAT_DATA_EN;#ifndef PIO	MMC_CMDAT |= MMC_CMDAT_MMC_DMA_EN; #endif/* 3. start clock */	if ( (ret = pxa_mmc_start_bus_clock( ctrlr )) )		goto error;    /* 4. wait for cmd to complete */	MMC_DEBUG( MMC_DEBUG_LEVEL3, "CMD18(0x%04x%04x)\n", argh, argl );	if ( (ret = pxa_mmc_complete_cmd( ctrlr, MMC_R1, TRUE )) )		goto error;    /* 6. transfer the data to the caller supplied buffer */	while ( transfer->cnt > 0 ) {		if ( (ret = pxa_mmc_read_buffer( ctrlr, transfer->cnt )) < 0 )			goto error;		if ( (ret = pxa_mmc_copy_from_buffer( ctrlr, transfer->type, transfer->buf, ret )) < 0 )			goto error;        		transfer->buf += ret;		transfer->cnt -= ret;	}    	pxa_mmc_set_state( ctrlr, PXA_MMC_FSM_END_IO );	if ( (ret = pxa_mmc_complete_io( ctrlr, transfer->cmd, transfer->mode )) )		goto error;    	ret = 0;error:	return ret;}/* Sequentally writes the data from a user buffer to the card */static int pxa_mmc_stream_write( mmc_controller_t ctrlr, mmc_data_transfer_req_t transfer ){	int ret = -EIO;	pxa_mmc_hostdata_t hostdata = (pxa_mmc_hostdata_t)ctrlr->host_data;	u16 argh = 0UL, argl = 0UL;	ssize_t size = 0;       // printk(KERN_EMERG"%s::%s\n\n", __FILE__, __FUNCTION__);    	__ENTER( "transfer: cmd=%d mode=%d type=%d blksz=%d "		 "nob=%d buf=%p cnt=%d addr=%Lx", transfer->cmd, 		transfer->mode, transfer->type, transfer->blksz, 		transfer->nob, transfer->buf, transfer->cnt, transfer->addr );	argh = transfer->addr >> 16;	argl = transfer->addr;/* 1. stop bus clock */	if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) ) 		goto error;/* 2. setup controller registers to start stream data transfer */	MMC_CMD = CMD(20); /* WRITE_DAT_UNTIL_STOP */	MMC_ARGH = argh;	MMC_ARGL = argl;	MMC_NOB = 0xffff;	MMC_BLKLEN = hostdata->iobuf.blksz;	MMC_CMDAT = MMC_CMDAT_R1|MMC_CMDAT_WRITE|MMC_CMDAT_STREAM|MMC_CMDAT_DATA_EN;#ifndef PIO	MMC_CMDAT |= MMC_CMDAT_MMC_DMA_EN; #endif/* 3. wait for cmd to complete */	MMC_DEBUG( MMC_DEBUG_LEVEL3, "CMD20(0x%04x%04x)\n", argh, argl );	if ( (ret = pxa_mmc_complete_cmd( ctrlr, MMC_R1, TRUE )) )		goto error;    /* 4. transfer the data to the caller supplied buffer */	while ( transfer->cnt > 0 ) {		size = (transfer->cnt < hostdata->iobuf.blksz) ?			transfer->cnt : hostdata->iobuf.blksz; 		if ( (ret = pxa_mmc_copy_to_buffer( ctrlr, 				transfer->type, transfer->buf, size )) < 0 )			goto error;        		if ( (ret = pxa_mmc_write_buffer( ctrlr, ret )) < 0 )			goto error;		transfer->buf += ret;		transfer->cnt -= ret;	}    	pxa_mmc_set_state( ctrlr, PXA_MMC_FSM_END_IO );	if ( (ret = pxa_mmc_complete_io( ctrlr, transfer->cmd, transfer->mode )) )		goto error;    	ret = 0;error:	return ret;}/* This procedure writes a data block to a card at a given address */static int pxa_mmc_write_block( mmc_controller_t ctrlr, mmc_data_transfer_req_t transfer ){	int ret = -ENODEV;	u16 argh = 0UL, argl = 0UL;       // printk(KERN_EMERG"IN %s::%s\n",__FILE__, __FUNCTION__);/* send CMD16 (SET_BLOCK_LEN) when requested block size is not the default * for the current card */  	if ( transfer->blksz != ctrlr->stack.selected->info.read_bl_len ) {		argh = transfer->blksz >> 16;		argl = transfer->blksz;		if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) ) 			goto error;    		MMC_CMD = CMD(16); /* SET_BLOCK_LEN */		MMC_ARGH = argh;		MMC_ARGL = argl;		MMC_CMDAT = MMC_CMDAT_R1 ;        		MMC_DEBUG( MMC_DEBUG_LEVEL3, "CMD16(0x%04x%04x)\n", argh, argl );		if ( (ret = pxa_mmc_complete_cmd( ctrlr, MMC_R1, FALSE )) )			goto error;	}               // printk(KERN_EMERG"send cmd(24): transfer->blksz is 0x%08x\n", transfer->blksz);/* CMD24 (WRITE_SINGLE_BLOCK) */	argh = transfer->addr >> 16;	argl = transfer->addr;	if ( (ret = pxa_mmc_stop_bus_clock( ctrlr )) )		goto error;    	MMC_CMD = CMD(24); /* WRITE_BLOCK */	MMC_ARGH = argh;	MMC_ARGL = argl;