/***************************************************************************
Project  :   TDA7540 Jig board 
Compiler : ST7 HiCross C (HiWARE)
Module   :  St72321.h
Version  :  V 1.0
Created  :  
Author   :  Jerry HE / ST-ShenZhen
Description
         -  MCU Related Register Headfile
Modified
	  - Jan.24th,2005    
***************************************************************************/

/*---------------------------------------------------------------------------
        Symbols for each flags used in ST72321 internal peripheral
        registers.
----------------------------------------------------------------------------*/
#define Port_A  0x00
#define Port_B  0x03
#define Port_C  0x06
#define Port_D  0x09
#define Port_E  0x0c
#define Port_F  0x0f

#define Tim1_C1 0x32
#define Tim1_C2 0x31
#define Tim1_S  0x33

#define Tim2_C2 0x41
#define Tim2_C1 0x42
#define Tim2_S  0x43

#define Adc_C   0x70       

/* -----Timer 1 Control Register 2---- */

#define TIM1_TCM1E        (Tim1_C2 * 8 + 7 - 7)
#define TIM1_TCM2E        (Tim1_C2 * 8 + 7 - 6)
#define TIM1_OPM          (Tim1_C2 * 8 + 7 - 5)
#define TIM1_PWM          (Tim1_C2 * 8 + 7 - 4)
#define TIM1_CC1          (Tim1_C2 * 8 + 7 - 3)
#define TIM1_CC0          (Tim1_C2 * 8 + 7 - 2)
#define TIM1_IEDG2        (Tim1_C2 * 8 + 7 - 1)
#define TIM1_EXEDG        (Tim1_C2 * 8 + 7 - 0)

/* -----Timer 1 Control Register 1---- */

#define TIM1_ICIE         (Tim1_C1 * 8 + 7 - 7)
#define TIM1_OCIE         (Tim1_C1 * 8 + 7 - 6)
#define TIM1_TOIE         (Tim1_C1 * 8 + 7 - 5)
#define TIM1_FOLV2        (Tim1_C1 * 8 + 7 - 4)
#define TIM1_FOLV1        (Tim1_C1 * 8 + 7 - 3)
#define TIM1_OLVL2        (Tim1_C1 * 8 + 7 - 2)
#define TIM1_IEDG1        (Tim1_C1 * 8 + 7 - 1)
#define TIM1_OLVL1        (Tim1_C1 * 8 + 7 - 0)

/* ------Timer 1 Status Register------ */

#define TIM1_ICF1         (Tim1_S * 8 + 7 - 7)
#define TIM1_OCF1         (Tim1_S * 8 + 7 - 6)
#define TIM1_TOF          (Tim1_S * 8 + 7 - 5)
#define TIM1_ICF2         (Tim1_S * 8 + 7 - 4)
#define TIM1_OCF2         (Tim1_S * 8 + 7 - 3)

/* -----Timer 2 Control Register 2---- */

#define TIM2_TCM1E        (Tim2_C2 * 8 + 7 - 7)
#define TIM2_TCM2E        (Tim2_C2 * 8 + 7 - 6)
#define TIM2_OPM          (Tim2_C2 * 8 + 7 - 5)
#define TIM2_PWM          (Tim2_C2 * 8 + 7 - 4)
#define TIM2_CC1          (Tim2_C2 * 8 + 7 - 3)
#define TIM2_CC0          (Tim2_C2 * 8 + 7 - 2)
#define TIM2_IEDG2        (Tim2_C2 * 8 + 7 - 1)
#define TIM2_EXEDG        (Tim2_C2 * 8 + 7 - 0)

/* -----Timer 2 Control Register 1---- */

#define TIM2_ICIE         (Tim2_C1 * 8 + 7 - 7)
#define TIM2_OCIE         (Tim2_C1 * 8 + 7 - 6)
#define TIM2_TOIE         (Tim2_C1 * 8 + 7 - 5)
#define TIM2_FOLV2        (Tim2_C1 * 8 + 7 - 4)
#define TIM2_FOLV1        (Tim2_C1 * 8 + 7 - 3)
#define TIM2_OLVL2        (Tim2_C1 * 8 + 7 - 2)
#define TIM2_IEDG1        (Tim2_C1 * 8 + 7 - 1)
#define TIM2_OLVL1        (Tim2_C1 * 8 + 7 - 0)

/* ------Timer 2 Status Register------ */

#define TIM2_ICF1         (Tim2_S * 8 + 7 - 7)
#define TIM2_OCF1         (Tim2_S * 8 + 7 - 6)
#define TIM2_TOF          (Tim2_S * 8 + 7 - 5)
#define TIM2_ICF2         (Tim2_S * 8 + 7 - 4)
#define TIM2_OCF2         (Tim2_S * 8 + 7 - 3)


/* ----ADC Control/Status Register---- */
#define ADC_COCO          (Adc_C * 8 + 7 - 7)
#define ADC_SPEED         (Adc_C * 8 + 7 - 6)
#define ADC_ADON          (Adc_C * 8 + 7 - 5)

/* ------MCC Control/Status Register------ */
#define MCO	7
#define SMS	4
#define OIE 1
#define OIF 0
#define FOSC_DIV_16		0x60		//CP0 and CP1 set 1, Fcpu divid by 16
#define TBC_50MS		0x0C		//50ms for 4MHz Fcpu 
//ARTCSR
#define TCE  3

//Used for I/O define
#pragma DATA_SEG SHORT ST7_PA
EXTR UByteField PA_DR;
#define P_I2CCLK  PA_DR.field.B7        //open drain output
#define P_I2CSDA PA_DR.field.B6         //open drain output
#define P_RDSDATA PA_DR.field.B1        //float input
#define P_RDSCLK PA_DR.field.B0         //float input

EXTR UByteField PA_DDR;
#define D_I2CCLK PA_DDR.field.B7
#define D_I2CSDA PA_DDR.field.B6
#define D_RDSDATA PA_DDR.field.B1
#define D_RDSCLK  PA_DDR.field.B0

EXTR UByteField  PA_OR;    /*        option register          */
#define O_I2CCLK PA_OR.field.B7
#define O_I2CSDA PA_OR.field.B6
#define O_RDSDATA PA_OR.field.B1
#define O_RDSCLK PA_OR.field.B0


#pragma DATA_SEG SHORT ST7_PB
EXTR UByteField PB_DR;
#define P_LCDEN  PB_DR.field.B0
#define P_LCDRW  PB_DR.field.B1
#define P_LCDRS  PB_DR.field.B2
#define P_FMVCC  PB_DR.field.B6


EXTR UByteField PB_DDR;
#define D_LCDEN  PB_DDR.field.B0
#define D_LCDRW  PB_DDR.field.B1
#define D_LCDRS  PB_DDR.field.B2
#define D_FMVCC  PB_DDR.field.B6

EXTR UByteField  PB_OR;    /*        option register          */
#define O_LCDEN  PB_OR.field.B0
#define O_LCDRW  PB_OR.field.B1
#define O_LCDRS  PB_OR.field.B2
#define O_FMVCC  PB_OR.field.B6


                                                        
#pragma DATA_SEG SHORT ST7_PC
EXTR UByteField PC_DR;
//#define P_RDSQUAL PC_DR.field.B7
#define P_LCDDB7 PC_DR.field.B7
#define P_LCDDB6 PC_DR.field.B6
#define P_LCDDB5 PC_DR.field.B5
#define P_LCDDB4 PC_DR.field.B4
#define P_LCDDB3 PC_DR.field.B3
#define P_LCDDB2 PC_DR.field.B2
#define P_LCDDB1 PC_DR.field.B1
#define P_LCDDB0 PC_DR.field.B0
EXTR UByteField PC_DDR;
//#define D_RDSQUAL PC_DDR.field.B7
#define D_LCDDB7 PC_DDR.field.B7
#define D_LCDDB6 PC_DDR.field.B6
#define D_LCDDB5 PC_DDR.field.B5
#define D_LCDDB4 PC_DDR.field.B4
#define D_LCDDB3 PC_DDR.field.B3
#define D_LCDDB2 PC_DDR.field.B2
#define D_LCDDB1 PC_DDR.field.B1
#define D_LCDDB0 PC_DDR.field.B0

EXTR UByteField  PC_OR;    /*        option register          */
#define O_LCDDB7 PC_OR.field.B7
#define O_LCDDB6 PC_OR.field.B6
#define O_LCDDB5 PC_OR.field.B5
#define O_LCDDB4 PC_OR.field.B4
#define O_LCDDB3 PC_OR.field.B3
#define O_LCDDB2 PC_OR.field.B2
#define O_LCDDB1 PC_OR.field.B1
#define O_LCDDB0 PC_OR.field.B0


#pragma DATA_SEG SHORT ST7_PD
EXTR UByteField PD_DR;
#define P_RDSQUAL PD_DR.field.B6