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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN"><html><head><link rel="STYLESHEET" type="text/css" href="wrs.css"><title> Data Link Layer Network Components </title></head><body bgcolor="FFFFFF"><p class="navbar" align="right"><a href="index.html"><img border="0" alt="[Contents]" src="icons/contents.gif"></a><a href="c-dll.html"><img border="0" alt="[Index]" src="icons/index.gif"></a><a href="c-dll.html"><img border="0" alt="[Top]" src="icons/top.gif"></a><a href="c-dll4.html"><img border="0" alt="[Prev]" src="icons/prev.gif"></a><a href="c-dll6.html"><img border="0" alt="[Next]" src="icons/next.gif"></a></p><font face="Helvetica, sans-serif" class="sans"><h3 class="H2"><i><a name="85549">3.5 Shared-Memory Network on the Backplane</a></i></h3></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="85551"> </a>The VxWorks network can also be used for communication among multiple processors on a common <i class="term">backplane.</i> In this case, data is passed through shared memory. This is implemented in the form of a standard network driver so that all the higher levels of network components are fully functional over this shared-memory "network." Thus, all the high-level network facilities provided over an Ethernet are also available over the shared-memory network.</p><dd><p class="Body"><a name="85553"> </a>A multiprocessor backplane bus contains a separate Internet network. Each shared-memory network has its own network/subnet number. As usual, each processor (host) on the shared-memory network has a unique Internet address. </p></dl></dl><dl class="margin"><dd><p class="table" callout><table border="0" cellpadding="0" cellspacing="0"><tr valign="top"><td valign="top" width="40"><br><img border="0" alt="*" src="icons/caution.gif"></td><td><hr><div class="CalloutCell"><a name="93470"><b class="symbol_UC"><font face="Helvetica, sans-serif" size="-1" class="sans">CAUTION: </font></b></a>This is different if you are using proxy ARP. See <a href="c-tcpip7.html#87225"><i class="title">4.7 ARP and Proxy ARP for Transparent Subnets</i></a> for additional information.</div></td></tr><tr valign="top"><td></td><td><hr></td></tr><tr valign="middle"><td colspan="20"></td></tr></table></p callout><dl class="margin"><dd><p class="Body"><a name="85569"> </a>In the example shown in <a href="c-dll5.html#85573">Figure 3-2</a>, two CPUs are on a backplane. The shared-memory network's Internet address is 161.27.0.0. Each CPU on the shared-memory network has a unique Internet address, 161.27.0.1 for <b class="symbol_lc">vx1</b> and 161.27.0.2 for <b class="symbol_lc">vx2</b>.<div class="frame"><h4 class="EntityTitle"><a name="85573"><font face="Helvetica, sans-serif" size="-1" class="sans">Figure 3-2: Shared-Memory Network</font></a></h4><dl class="margin"><div class="Anchor"><a name="85595"> </a><img class="figure" border="0" src="images/c-dlla2.gif"></div></dl></div></p><dd><p class="Body"><a name="85597"> </a>The routing capabilities of the VxWorks IP layer allow processors on a shared-memory network to reach systems on other networks over a <i class="term">gateway</i> processor on the shared-memory network. The gateway processor has connections to both the shared-memory network and an external network. These connections allow higher-level protocols to transmit data between any processor on the shared-memory network and any other host or target system on the external network. </p><dd><p class="Body"><a name="85598"> </a>The low-level data transfer mechanism of the shared-memory network driver is also available directly. This allows alternative protocols to be run over the shared-memory network in addition to the standard ones.</p><dd><p class="Body"><a name="85599"> </a>The following features allow the VxWorks shared-memory network driver to send network packets from one processor on the backplane to another:</p></dl><dl class="margin"><p class="listspace"><ul class="Bullet" type="disc"><li><a name="85600"> </a>Packets are transferred across the backplane through a pool of <i class="term">shared memory</i> that can be accessed by all processors on the backplane.</li></ul></p><p class="listspace"><ul class="Bullet" type="disc"><li><a name="85602"> </a>Access to the shared-memory pool is interlocked by use of a test-and-set instruction.</li></ul></p><p class="listspace"><ul class="Bullet" type="disc"><li><a name="85603"> </a>Processors can poll the shared-memory data structures for input packets receive notification of packet arrival through interrupts.</li></ul></p></dl><dl class="margin"><dd><p class="Body"><a name="85604"> </a>The shared-memory network is configured by various configuration constants and by parameters specified to the VxWorks boot ROMs. The following sections give the details of the backplane network operation and configuration.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H3"><i><a name="85605">3.5.1 The Backplane Shared-Memory Pool</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="85606"> </a>The basis of the VxWorks shared-memory network is the <i class="term">shared-memory pool.</i> This is a contiguous block of memory that must be accessible to all processors on the backplane. Typically this memory is either part of one of the processors' on-board, dual-ported memory, or a separate memory board.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="85607">Backplane Processor Numbers</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="85609"> </a>The processors on the backplane are each assigned a unique <i class="term">backplane processor number</i> starting with 0. The assignment of numbers is arbitrary, except for processor 0, which by convention is the shared-memory network master, described in the next section.</p><dd><p class="Body"><a name="85610"> </a>The processor numbers are established by the parameters supplied to the boot ROMs when the system is booted. These parameters can be burned into ROM, set in the processor's NVRAM (if available), or entered manually.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="85611">The Shared-Memory Network Master: Processor 0</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="85613"> </a>One of the processors on the backplane is the <i class="term">shared-memory network master.</i> The shared-memory network master has the following responsibilities:</p></dl><dl class="margin"><p class="listspace"><ul class="Bullet" type="disc"><li><a name="85615"> </a>Initializing the shared-memory pool and the <i class="term">shared-memory</i> <i class="term">anchor</i>.</li></ul></p><p class="listspace"><ul class="Bullet" type="disc"><li><a name="85617"> </a>Maintaining the <i class="term">shared-memory heartbeat</i>.</li></ul></p><p class="listspace"><ul class="Bullet" type="disc"><li><a name="85618"> </a>Functioning (usually) as the gateway to the external (Ethernet) network.</li></ul></p><p class="listspace"><ul class="Bullet" type="disc"><li><a name="85619"> </a>Allocating the shared-memory pool from its dual-ported memory (in some configurations).</li></ul></p></dl><dl class="margin"><dd><p class="Body"><a name="85620"> </a>No processor can use the shared-memory network until the master has initialized it. However, the master processor is <i class="emphasis">not</i> involved in the actual transmission of packets on the backplane between other processors. After the shared-memory pool is initialized, the processors, including the master, are all peers.</p><dd><p class="Body"><a name="85621"> </a>The configuration module <b class="file">target/src/config/usrNetwork.c</b> sets the processor number of the master to 0. The master usually boots from the external (Ethernet) network directly. The master has two Internet addresses in the system: its Internet address on the Ethernet, and its address on the shared-memory network. See the reference entry for <b class="library">usrConfig</b>.</p><dd><p class="Body"><a name="85622"> </a>The other processors on the backplane boot indirectly over the shared-memory network, using the master as the gateway. They have only an Internet address on the shared-memory network. These processors specify the shared-memory network interface, <b class="symbol_lc">sm</b>, as the boot device in the boot parameters.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="85624">The Shared-Memory Anchor</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="85626"> </a>The location of the shared-memory pool depends on the system configuration. In many situations, you want to allocate the shared memory at run-time rather than fixing its location at the time the system is built.</p><dd><p class="Body"><a name="85627"> </a>Of course, all processors on the shared-memory network must be able to access the shared-memory pool, even if its location is not assigned at compile time. The shared-memory anchor serves as a common point of reference for all processors. The anchor is a small data structure assigned at a fixed location at compile time. This location is usually in low memory of the dual-ported memory of one of the processors. Sometimes the anchor structure is stored at some fixed address on the separate memory board.</p><dd><p class="Body"><a name="85628"> </a>The anchor contains a pointer to the actual shared-memory pool. The master sets this pointer during initialization. The value of the pointer to the shared-memory pool is actually an offset from the anchor itself. Thus, the anchor and pool must be in the same address space so that the offset is valid for all processors.</p><dd><p class="Body"><a name="85630"> </a>The backplane anchor address is established by configuration constants or by boot parameters. For the shared-memory network master, the anchor address is assigned in the master's configuration at the time the system image is built. The shared memory anchor address, <i class="emphasis">as seen by the master</i>, is also set during configuration. The relevant configuration macro is <b class="symbol_UC">SM_ANCHOR_ADRS</b>.</p><dd><p class="Body"><a name="85632"> </a>For the other processors on the shared-memory network, a default anchor address can also be assigned during configuration in the same way. However, this requires burning boot ROMs with that configuration, because the other processors must, at first, boot from the shared-memory network. For this reason, the anchor address can also be specified in the boot parameters if the shared-memory network is the boot device. To do this, enter the address (separated by an equal sign, "=") after the shared-memory network boot device specifier <b>sm</b>. For example, the following line sets the anchor address to 0x800000: </p><dl class="margin"><dd><pre class="Code2"><b><a name="85633">boot device: sm=0x800000</a></b></pre></dl><dd><p class="Body"><a name="85634"> </a>In this case, this is the address of the anchor <i class="emphasis">as seen by the processor being booted</i>.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="85636">The Shared-Memory Heartbeat</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="85638"> </a>The processors on the shared-memory network cannot communicate over that network until the shared-memory pool initialization is finished. To let the other processors know when the backplane is "alive," the master maintains a <i class="term">shared-memory heartbeat</i>. This heartbeat is a counter that is incremented by the master once per second. Processors on the shared-memory network determine that the shared-memory network is alive by watching the heartbeat for a few seconds.</p><dd><p class="Body"><a name="85639"> </a>The shared-memory heartbeat is located in the first 4-byte word of the shared-memory pool. The offset of the shared-memory pool is the fifth 4-byte word in the anchor, as shown in <a href="c-dll5.html#85646">Figure 3-3</a>. <div class="frame"><h4 class="EntityTitle"><a name="85646"><font face="Helvetica, sans-serif" size="-1" class="sans">Figure 3-3: Shared-Memory Heartbeat</font></a></h4><dl class="margin"><div class="Anchor"><a name="85673"> </a><img class="figure" border="0" src="images/c-dlla3.gif"></div></dl></div></p><dd><p class="Body"><a name="85674"> </a>Thus, if the anchor were located at 0x800000:</p><dl class="margin"><dd><pre class="Code2"><b><a name="85675"></b><tt class="output">[VxWorks Boot]:</tt><b> d 0x800000 </b><tt class="output">800000: 8765 4321 0000 0001 0000 0000 0000 002c *.eC!...........,*</tt><b> </b><tt class="output">800010: 0000 0170 0000 0000 0000 0000 0000 0000 *...p............* 800020: 0000 0000 0000 0000 0000 0000 0000 0000 *................* </tt><b></a></b></pre></dl><dd><p class="Body"><a name="85679"> </a>The offset to the shared-memory pool is 0x170. To view the start of the shared-memory pool, display 0x800170:</p><dl class="margin"><dd><pre class="Code2"><b><a name="85680"></b><tt class="output">[VxWorks Boot]:</tt><b> d 0x800170 </b><tt class="output">800170: 0000 0050 0000 0000 0000 0bfc 0000 0350 *...P...........P*</tt><b></a></b></pre></dl><dd><p class="Body"><a name="85682"> </a>In this example, the value of the shared-memory heartbeat is 0x50. Examine this location again to determine whether the network is alive. If the value has changed, the network is alive.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="85684">Shared-Memory Location</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="85686"> </a>As mentioned previously, shared memory is assigned a fixed location at compile time or it is allocated dynamically at run-time. The location is determined by the value of the shared memory size set during configuration (configuration constant: <b class="symbol_UC">SM_MEM_ADRS</b>). This constant can be specified as follows:</p></dl><dl class="margin"><p class="listspace"><ul class="Bullet" type="disc"><li><a name="85688"> </a><b class="symbol_UC">NONE</b> (-1) means that the shared-memory pool is to be dynamically allocated from the master's on-board dual-ported memory.</li></ul></p><p class="listspace"><ul class="Bullet" type="disc"><li><a name="85689"> </a>An absolute address that is <i class="emphasis">different</i> from the anchor address. The shared memory anchor address (configuration constant: <b class="symbol_UC">SM_ANCHOR_ADRS</b>) indicates that the shared-memory pool starts at that fixed address.</li></ul></p><p class="listspace"><ul class="Bullet" type="disc"><li><a name="85691"> </a>For convenience, an absolute address that is the <i class="emphasis">same</i> as the anchor address means the shared-memory pool starts immediately after the anchor data structure; the size of that structure need not be known in advance.</li></ul></p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="85692">Shared Memory Size</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="85695"> </a>The size of the shared-memory pool is set during configuration. The relevant configuration macro is <b class="symbol_UC">SM_MEM_SIZE</b>.</p><dd><p class="Body"><a name="85696"> </a>The size required for the shared-memory pool depends on the number of processors and the expected traffic. There is less than 2KB of overhead for data structures. After that, the shared-memory pool is divided into 2KB packets. Thus, the maximum number of packets available on the backplane network is (<i class="textVariable">poolsize</i> - 2KB) / 2KB. A reasonable minimum is 64KB. A configuration with a large number of processors on one backplane and many simultaneous connections can require as much as 512KB. Having too small a pool slows down communications.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="85698">On-Board and Off-Board Options</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="85700"> </a>The configuration of VxWorks includes a conditional compilation constant that makes it easy to select a pair of typical configurations, for instance between an <i class="emphasis">off-board</i> shared-memory pool and an <i class="emphasis">on-board</i> shared memory pool. The relevant configuration macro is <b class="symbol_UC">SM_OFF_BOARD</b>.</p><dd><p class="Body"><a name="85703"> </a>A typical <i class="term">off-board</i> configuration establishes the backplane anchor and memory pool at an absolute address of 0x800000 on a separate memory board with a pool size of 512KB.</p><dd><p class="Body"><a name="85705"> </a>The <i class="term">on-board</i> configuration establishes the shared-memory anchor at a low address in the master processor's dual-ported memory. The shared-memory pool size is set to 64KB allocated from the master's own memory at run time. </p></dl></dl><dl class="margin"><dd><p class="table" callout><table border="0" cellpadding="0" cellspacing="0"><tr valign="top"><td valign="top" width="40"><br><img border="0" alt="*" src="icons/note.gif"></td><td><hr><div class="CalloutCell"><a name="91592"><b class="symbol_UC"><font face="Helvetica, sans-serif" size="-1" class="sans">NOTE: </font></b></a>These configurations are provided as examples. Change them to suit your needs.</div></td></tr><tr valign="top"><td></td><td><hr></td></tr><tr valign="middle"><td colspan="20"></td></tr></table></p callout><dl class="margin"><dd><p class="Body"><a name="85714"> </a>Because the shared-memory pool is accessed by all processors on the backplane, that memory must be configured as non-cacheable. On some systems, this requires that you change the <b class="symbol_lc">sysPhysMemDesc[ ]</b> table in<b class="file">sysLib.c</b>. Specifically, any board whose MMU is enabled (the default) must disable caching for off-board memory. Fortunately, if the VME address space used for the shared-memory pool already has a virtual-to-physical mapping in the table, the memory is already marked non-cacheable. Otherwise, you must add the appropriate mapping (with caching disabled). </p><dd><p class="Body"><a name="85717"> </a>For the MC680<i class="textVariable">x</i>0 family of processors, virtual addresses must equal physical addresses. For the 68030, if the MMU is off, caching must be turned off globally; see the reference entry for <b class="library">cacheLib</b>. Note that the default for all BSPs is to have their VME bus access set to non-cacheable in <b class="symbol_lc">sysPhysMemDesc[ ]</b>. See <i class="title">VxWorks Programmer's Guide: Virtual Memory Interface</i>. </p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="85719">Test-and-Set to Shared Memory</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="85721"> </a>Unless some form of mutual exclusion is provided, multiple processors can simultaneously access certain critical data structures of the shared-memory pool and cause fatal errors. The VxWorks shared-memory network uses an indivisible test-and-set instruction to obtain exclusive use of a shared-memory data structure. This translates into a <i class="term">read-modify-write</i> (RMW) cycle on the backplane bus.</p><dd><p class="Body"><a name="85723"> </a>It is important that the selected shared memory supports the RMW cycle on the bus and guarantee the indivisibility of such cycles. This is especially problematic if the memory is dual-ported, as the memory must then also lock out one port during a RMW cycle on the other.</p><dd><p class="Body"><a name="85724"> </a>Some processors do not support RMW indivisibly in hardware, but do have software hooks to provide the capability. For example, some processor boards have a flag that can be set to prevent the board from releasing the backplane bus, after it is acquired, until that flag is cleared. You can implement these techniques for a processor in the <b class="routine"><i class="routine">sysBusTas</i></b><b>( )</b>routine of the system-dependent library <b class="library">sysLib.c</b>. The shared-memory network driver calls this routine to set up mutual exclusion on shared-memory data structures.</p></dl></dl><dl class="margin"><dd><p class="table" callout><table border="0" cellpadding="0" cellspacing="0"><tr valign="top"><td valign="top" width="40"><br><img border="0" alt="*" src="icons/caution.gif"></td><td><hr><div class="CalloutCell"><a name="93480"><b class="symbol_UC"><font face="Helvetica, sans-serif" size="-1" class="sans">CAUTION: </font></b></a>Configure the shared memory test-and-set type for VxWorks (configuration constant: <b class="symbol_UC">SM_TAS_TYPE</b>) to either <b class="symbol_UC">SM_TAS_SOFT</b> or <b class="symbol_UC">SM_TAS_HARD</b>. If even one processor on the backplane lacks hardware test and set, all processors in the backplane must use the software test and set (<b class="symbol_UC">SM_TAS_SOFT</b>). </div></td>?? 快捷鍵說明
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