?? s3c44b0x.s
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;/*****************************************************************************/
;/* S3C44B0X.S: Startup file for Hello Example */
;/*****************************************************************************/
;/* <<< Use Configuration Wizard in Context Menu >>> */
;/*****************************************************************************/
;/* This file is part of the uVision/ARM development tools. */
;/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */
;/* This software may only be used under the terms of a valid, current, */
;/* end user licence from KEIL for a compatible version of KEIL software */
;/* development tools. Nothing else gives you the right to use this software. */
;/*****************************************************************************/
; *** Startup Code (executed after Reset) ***
; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1F
I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
;// <h> Stack Configuration (Stack Sizes in Bytes)
;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
;// </h>
UND_Stack_Size EQU 0x00000000
SVC_Stack_Size EQU 0x00000008
ABT_Stack_Size EQU 0x00000000
FIQ_Stack_Size EQU 0x00000000
IRQ_Stack_Size EQU 0x00000080
USR_Stack_Size EQU 0x00000400
Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
FIQ_Stack_Size + IRQ_Stack_Size + USR_Stack_Size)
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
Stack_Top EQU Stack_Mem + Stack_Size
;// <h> Heap Configuration
;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
;// </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
Heap_Mem SPACE Heap_Size
; CPU Wrapper and Bus Priorities definitions
CPUW_BASE EQU 0x01C00000 ; CPU Wrapper Base Address
SYSCFG_OFS EQU 0x00 ; SYSCFG Offset
NCACHBE0_OFS EQU 0x04 ; NCACHBE0 Offset
NCACHBE1_OFS EQU 0x08 ; NCACHBE0 Offset
BUSP_BASE EQU 0x01C40000 ; Bus Priority Base Address
SBUSCON_OFS EQU 0x00 ; SBUSCON Offset
;// <e> CPU Wrapper and Bus Priorities
;// <h> CPU Wrapper
;// <o1.0> SE: Stall Enable
;// <o1.1..2> CM: Cache Mode
;// <0=> Disable Cache (8kB SRAM)
;// <1=> Half Cache Enable (4kB Cache, 4kB SRAM)
;// <2=> Reserved
;// <3=> Full Cache Enable (8kB Cache)
;// <o1.3> WE: Write Buffer Enable
;// <o1.4> RSE: Read Stall Enable
;// <o1.5> DA: Data Abort <0=> Enable <1=> Disable
;// <h> Non-cacheable Area 0
;// <o2.0..15> Start Address <0x0-0x0FFFF000:0x1000><#/0x1000>
;// <i> SA = (Start Address) / 4k
;// <o2.16..31> End Address + 1 <0x0-0x10000000:0x1000><#/0x1000>
;// <i> SE = (End Address + 1) / 4k
;// </h>
;// <h> Non-cacheable Area 1
;// <o3.0..15> Start Address <0x0-0x0FFFF000:0x1000><#/0x1000>
;// <i> SA = (Start Address) / 4k
;// <o3.16..31> End Address + 1 <0x0-0x10000000:0x1000><#/0x1000>
;// <i> SE = (End Address + 1) / 4k
;// </h>
;// </h>
;// <h> Bus Priorities
;// <o4.31> FIX: Fixed Priorities
;// <o4.6..7> LCD_DMA <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th
;// <o4.4..5> ZDMA <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th
;// <o4.2..3> BDMA <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th
;// <o4.0..1> nBREQ <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th
;// </h>
;// </e>
SYS_SETUP EQU 1
SYSCFG_Val EQU 0x00000006
NCACHBE0_Val EQU 0x00000000
NCACHBE1_Val EQU 0x00000000
SBUSCON_Val EQU 0x80001B1B
;// <e> Vectored Interrupt Mode (for IRQ)
;// <o1.25> EINT0 <i> External Interrupt 0
;// <o1.24> EINT1 <i> External Interrupt 1
;// <o1.23> EINT2 <i> External Interrupt 2
;// <o1.22> EINT3 <i> External Interrupt 3
;// <o1.21> EINT4567 <i> External Interrupt 4/5/6/7
;// <o1.20> TICK <i> RTC Time Tick Interrupt
;// <o1.19> ZDMA0 <i> General DMA0 Interrupt
;// <o1.18> ZDMA1 <i> General DMA1 Interrupt
;// <o1.17> BDMA0 <i> Bridge DMA0 Interrupt
;// <o1.16> BDMA1 <i> Bridge DMA1 Interrupt
;// <o1.15> WDT <i> Watchdog Timer Interrupt
;// <o1.14> UERR01 <i> UART0/1 Error Interrupt
;// <o1.13> TIMER0 <i> Timer0 Interrupt
;// <o1.12> TIMER1 <i> Timer1 Interrupt
;// <o1.11> TIMER2 <i> Timer2 Interrupt
;// <o1.10> TIMER3 <i> Timer3 Interrupt
;// <o1.9> TIMER4 <i> Timer4 Interrupt
;// <o1.8> TIMER5 <i> Timer5 Interrupt
;// <o1.7> URXD0 <i> UART0 Rx Interrupt
;// <o1.6> URXD1 <i> UART1 Rx Interrupt
;// <o1.5> IIC <i> IIC Interrupt
;// <o1.4> SIO <i> SIO Interrupt
;// <o1.3> UTXD0 <i> UART0 Tx Interrupt
;// <o1.2> UTXD1 <i> UART1 Tx Interrupt
;// <o1.1> RTC <i> RTC Alarm Interrupt
;// <o1.0> ADC <i> ADC EOC Interrupt
;// </e>
VIM_SETUP EQU 1
VIM_CFG EQU 0x00024080
; Clock Management definitions
CLK_BASE EQU 0x01D80000 ; Clock Base Address
PLLCON_OFS EQU 0x00 ; PLLCON Offset
CLKCON_OFS EQU 0x04 ; CLKCON Offset
CLKSLOW_OFS EQU 0x08 ; CLKSLOW Offset
LOCKTIME_OFS EQU 0x0C ; LOCKTIME Offset
;// <e> Clock Management
;// <h> PLL Settings
;// <i> Fpllo = (m * Fin) / (p * 2^s), 20MHz < Fpllo < 66MHz
;// <o1.12..19> MDIV: Main divider <0x0-0xFF>
;// <i> m = MDIV + 8
;// <o1.4..9> PDIV: Pre-divider <0x0-0x3F>
;// <i> p = PDIV + 2, 1MHz <= Fin/p < 2MHz
;// <o1.0..1> SDIV: Post Divider <0x0-0x03>
;// <i> s = SDIV, Fpllo * 2^s < 170MHz
;// <o4.0..11> LTIME CNT: PLL Lock Time Count <0x0-0x0FFF>
;// </h>
;// <h> Master Clock
;// <i> PLL Clock: Fout = Fpllo
;// <i> Slow Clock: Fout = Fin / (2 * SLOW_VAL), SLOW_VAL > 0
;// <i> Slow Clock: Fout = Fin, SLOW_VAL = 0
;// <o3.5> PLL_OFF: PLL Off
;// <i> PLL is turned Off only when SLOW_BIT = 1
;// <o3.4> SLOW_BIT: Slow Clock
;// <o3.0..3> SLOW_VAL: Slow Clock divider <0x0-0x0F>
;// </h>
;// <h> Clock Generation
;// <o2.14> IIS <0=> Disable <1=> Enable
;// <o2.13> IIC <0=> Disable <1=> Enable
;// <o2.12> ADC <0=> Disable <1=> Enable
;// <o2.11> RTC <0=> Disable <1=> Enable
;// <o2.10> GPIO <0=> Disable <1=> Enable
;// <o2.9> UART1 <0=> Disable <1=> Enable
;// <o2.8> UART0 <0=> Disable <1=> Enable
;// <o2.7> BDMA0,1 <0=> Disable <1=> Enable
;// <o2.6> LCDC <0=> Disable <1=> Enable
;// <o2.5> SIO <0=> Disable <1=> Enable
;// <o2.4> ZDMA0,1 <0=> Disable <1=> Enable
;// <o2.3> PWMTIMER <0=> Disable <1=> Enable
;// </h>
;// </e>
CLK_SETUP EQU 1
PLLCON_Val EQU 0x00070061
CLKCON_Val EQU 0x00007FF8
CLKSLOW_Val EQU 0x00000009
LOCKTIME_Val EQU 0x00000FFF
; Watchdog Timer definitions
WT_BASE EQU 0x01D30000 ; WT Base Address
WTCON_OFS EQU 0x00 ; WTCON Offset
WTDAT_OFS EQU 0x04 ; WTDAT Offset
WTCNT_OFS EQU 0x08 ; WTCNT Offset
;// <e> Watchdog Timer
;// <o1.5> Watchdog Timer Enable/Disable
;// <o1.0> Reset Enable/Disable
;// <o1.2> Interrupt Enable/Disable
;// <o1.3..4> Clock Select
;// <0=> 1/16 <1=> 1/32 <2=> 1/64 <3=> 1/128
;// <i> Clock Division Factor
;// <o1.8..15> Prescaler Value <0x0-0xFF>
;// <o2.0..15> Time-out Value <0x0-0xFFFF>
;// </e>
WT_SETUP EQU 1
WTCON_Val EQU 0x00008000
WTDAT_Val EQU 0x00008000
; Memory Controller definitions
MC_BASE EQU 0x01C80000 ; Memory Controller Base Address
;// <e> Memory Controller
MC_SETUP EQU 1
;// <h> Bank 0
;// <o0.0..1> PMC: Page Mode Configuration
;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data
;// <o0.2..3> Tpac: Page Mode Access Cycle
;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks
;// <o0.4..5> Tcah: Address Holding Time after nGCSn
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o0.6..7> Toch: Chip Select Hold on nOE
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o0.8..10> Tacc: Access Cycle
;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks
;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks
;// <o0.11..12> Tcos: Chip Select Set-up nOE
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o0.13..14> Tacs: Address Set-up before nGCSn
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// </h>
;//
;// <h> Bank 1
;// <o8.4..5> DW: Data Bus Width
;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd
;// <o8.6> WS: WAIT Status
;// <0=> WAIT Disable
;// <1=> WAIT Enable
;// <o8.7> ST: SRAM Type
;// <0=> Not using UB/LB
;// <1=> Using UB/LB
;// <o1.0..1> PMC: Page Mode Configuration
;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data
;// <o1.2..3> Tpac: Page Mode Access Cycle
;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks
;// <o1.4..5> Tcah: Address Holding Time after nGCSn
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o1.6..7> Toch: Chip Select Hold on nOE
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o1.8..10> Tacc: Access Cycle
;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks
;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks
;// <o1.11..12> Tcos: Chip Select Set-up nOE
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o1.13..14> Tacs: Address Set-up before nGCSn
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// </h>
;//
;// <h> Bank 2
;// <o8.8..9> DW: Data Bus Width
;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd
;// <o8.10> WS: WAIT Status
;// <0=> WAIT Disable
;// <1=> WAIT Enable
;// <o8.11> ST: SRAM Type
;// <0=> Not using UB/LB
;// <1=> Using UB/LB
;// <o2.0..1> PMC: Page Mode Configuration
;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data
;// <o2.2..3> Tpac: Page Mode Access Cycle
;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks
;// <o2.4..5> Tcah: Address Holding Time after nGCSn
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o2.6..7> Toch: Chip Select Hold on nOE
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o2.8..10> Tacc: Access Cycle
;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks
;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks
;// <o2.11..12> Tcos: Chip Select Set-up nOE
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o2.13..14> Tacs: Address Set-up before nGCSn
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// </h>
;//
;// <h> Bank 3
;// <o8.12..13> DW: Data Bus Width
;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd
;// <o8.14> WS: WAIT Status
;// <0=> WAIT Disable
;// <1=> WAIT Enable
;// <o8.15> ST: SRAM Type
;// <0=> Not using UB/LB
;// <1=> Using UB/LB
;// <o3.0..1> PMC: Page Mode Configuration
;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data
;// <o3.2..3> Tpac: Page Mode Access Cycle
;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks
;// <o3.4..5> Tcah: Address Holding Time after nGCSn
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o3.6..7> Toch: Chip Select Hold on nOE
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o3.8..10> Tacc: Access Cycle
;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks
;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks
;// <o3.11..12> Tcos: Chip Select Set-up nOE
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o3.13..14> Tacs: Address Set-up before nGCSn
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// </h>
;//
;// <h> Bank 4
;// <o8.16..17> DW: Data Bus Width
;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd
;// <o8.18> WS: WAIT Status
;// <0=> WAIT Disable
;// <1=> WAIT Enable
;// <o8.19> ST: SRAM Type
;// <0=> Not using UB/LB
;// <1=> Using UB/LB
;// <o4.0..1> PMC: Page Mode Configuration
;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data
;// <o4.2..3> Tpac: Page Mode Access Cycle
;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks
;// <o4.4..5> Tcah: Address Holding Time after nGCSn
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o4.6..7> Toch: Chip Select Hold on nOE
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o4.8..10> Tacc: Access Cycle
;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks
;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks
;// <o4.11..12> Tcos: Chip Select Set-up nOE
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o4.13..14> Tacs: Address Set-up before nGCSn
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// </h>
;//
;// <h> Bank 5
;// <o8.20..21> DW: Data Bus Width
;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd
;// <o8.22> WS: WAIT Status
;// <0=> WAIT Disable
;// <1=> WAIT Enable
;// <o8.23> ST: SRAM Type
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