LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY AD0809 IS
	PORT(   
     SYSCLOCK : IN STD_LOGIC;
	       OE : OUT STD_LOGIC;
	     WR_n : OUT STD_LOGIC;
	     ADDR : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
			D : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	        Q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
	
		EOC_0 : IN STD_LOGIC;
		CLK_0 : OUT STD_LOGIC;
      RST_n_0 : OUT STD_LOGIC;
		 CS_0 : OUT STD_LOGIC;
	 HOLD_A_0 : OUT STD_LOGIC;
	 HOLD_B_0 : OUT STD_LOGIC;
	 HOLD_C_0 : OUT STD_LOGIC;	
	 BYTE_n_0 : OUT STD_LOGIC;
	    ADD_0 : OUT STD_LOGIC;
	
		EOC_1 : IN STD_LOGIC;
		CLK_1 : OUT STD_LOGIC;
      RST_n_1 : OUT STD_LOGIC;
		 CS_1 : OUT STD_LOGIC;
	 HOLD_A_1 : OUT STD_LOGIC;
	 HOLD_B_1 : OUT STD_LOGIC;
	 HOLD_C_1 : OUT STD_LOGIC;	
	 BYTE_n_1 : OUT STD_LOGIC;
	    ADD_1 : OUT STD_LOGIC );

END AD0809;

ARCHITECTURE behav OF AD0809 IS

COMPONENT ADLL_ADS
PORT(
	inclk0		:IN 	STD_LOGIC;
	c0			:OUT 	STD_LOGIC		--40MHz 
	);
END COMPONENT;

TYPE    states IS (st0,st1,st2,st3,st4,st5,st6,st7,st8,st9,st10,
				   st11,st12,st13,st14,st15,st16,st17,st18,st19,st20);
SIGNAL  current_state, next_state: states :=st0;
SIGNAL  REGL : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL  RD : STD_LOGIC;
SIGNAL 	ADS8364_CLK	: STD_LOGIC;
SIGNAL 	SYSCLK : STD_LOGIC;
SIGNAL  START : STD_LOGIC;


BEGIN
      ADD_0 <= '0';
	  BYTE_n_0 <= '0';
	  RST_n_0 <= '1';
	
	  ADD_1 <= '0';
	  BYTE_n_1 <= '0';
	  RST_n_1 <= '1';
	
	  WR_n <= '1';
	
	  ADDR(2 DOWNTO 0) <= "111";
	  HOLD_A_0 <= START;
	  HOLD_B_0 <= START;
	  HOLD_C_0 <= START;
	  HOLD_A_1 <= START;
	  HOLD_B_1 <= START;
	
	  Q  <= REGL; OE <= RD;
	
ADCLK: PROCESS(SYSCLK)
		VARIABLE COUNT: STD_LOGIC_VECTOR(3 DOWNTO 0); 
	   BEGIN
		 IF RISING_EDGE(SYSCLK) THEN 
			IF COUNT="0100" THEN 			
			COUNT := (OTHERS => '0');
			ADS8364_CLK<=NOT ADS8364_CLK;
			ELSE COUNT :=COUNT + 1;
			END IF;
		END IF;
END PROCESS ADCLK;
			
	CLK_0 <= ADS8364_CLK;
	CLK_1 <= ADS8364_CLK;
	
COM: PROCESS(current_state,EOC_0)
     VARIABLE COUNT1: STD_LOGIC_VECTOR(1 DOWNTO 0);
	  BEGIN
	  	CASE  current_state IS
		WHEN st0 =>CS_0<= '1'; CS_1<= '1'; START <= '1'; RD <= '1'; next_state <= st1;
		WHEN st1 =>CS_0<= '1'; CS_1<= '1'; START <= '0'; RD <= '1'; next_state <= st2;
		WHEN st2 =>CS_0<= '1'; CS_1<= '1'; START <= '1'; RD <= '1'; 
			IF (COUNT1 = "11") THEN
			   COUNT1 := "00";
			   next_state <= st3;
			ELSIF (EOC_0 = '1' AND EOC_0 'EVENT) THEN 
			   COUNT1 := COUNT1 + 1;
			   next_state <=st2;
			END IF;
		WHEN st3 =>CS_0<= '0'; CS_1<= '1'; START <= '1'; RD <= '0'; next_state <= st4;
		WHEN st4 =>CS_0<= '0'; CS_1<= '1'; START <= '1'; RD <= '1'; next_state <= st5;
		WHEN st5 =>CS_0<= '0'; CS_1<= '1'; START <= '1'; RD <= '0'; next_state <= st6;
		WHEN st6 =>CS_0<= '0'; CS_1<= '1'; START <= '1'; RD <= '1'; next_state <= st7;
		WHEN st7 =>CS_0<= '0'; CS_1<= '1'; START <= '1'; RD <= '0'; next_state <= st8;
		WHEN st8 =>CS_0<= '0'; CS_1<= '1'; START <= '1'; RD <= '1'; next_state <= st9;
		WHEN st9 =>CS_0<= '0'; CS_1<= '1'; START <= '1'; RD <= '0'; next_state <= st10;
		WHEN st10 =>CS_0<= '0'; CS_1<= '1'; START <= '1'; RD <= '1'; next_state <= st11;
		WHEN st11 =>CS_0<= '0'; CS_1<= '1'; START <= '1'; RD <= '0'; next_state <= st12;
		WHEN st12 =>CS_0<= '0'; CS_1<= '1'; START <= '1'; RD <= '1'; next_state <= st13;
		WHEN st13 =>CS_0<= '0'; CS_1<= '1'; START <= '1'; RD <= '0'; next_state <= st14;
		WHEN st14 =>CS_0<= '0'; CS_1<= '1'; START <= '1'; RD <= '1'; next_state <= st15;

		WHEN st15 =>CS_0<= '1'; CS_1<= '0'; START <= '1'; RD <= '0'; next_state <= st16;
		WHEN st16 =>CS_0<= '1'; CS_1<= '0'; START <= '1'; RD <= '1'; next_state <= st17;
		WHEN st17 =>CS_0<= '1'; CS_1<= '0'; START <= '1'; RD <= '0'; next_state <= st18;
		WHEN st18 =>CS_0<= '1'; CS_1<= '0'; START <= '1'; RD <= '1'; next_state <= st19;
		WHEN st19 =>CS_0<= '1'; CS_1<= '0'; START <= '1'; RD <= '0'; next_state <= st20;
		WHEN st20 =>CS_0<= '1'; CS_1<= '0'; START <= '1'; RD <= '1'; next_state <= st0;
		WHEN OTHERS => next_state <= st0;
		END CASE;
END PROCESS COM;

REG: PROCESS(ADS8364_CLK)
     BEGIN
		IF (ADS8364_CLK 'EVENT AND ADS8364_CLK = '0') THEN 
			current_state <= next_state;
		END IF;
END PROCESS REG;

LATCH1: PROCESS(RD)
		BEGIN
		IF RD = '0'  THEN 
			REGL <= D;
	    ELSE
	        REGL <= "ZZZZZZZZZZZZZZZZ";
		END IF;
END PROCESS LATCH1;

	U1:ADLL_ADS
	PORT MAP(
		inclk0		=>	SYSCLOCK,
		c0			=>	SYSCLK);

END behav;