+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Total logic elements              ; 251     ;
; Total combinational functions     ; 220     ;
;     -- Total 4-input functions    ; 115     ;
;     -- Total 3-input functions    ; 37      ;
;     -- Total 2-input functions    ; 30      ;
;     -- Total 1-input functions    ; 38      ;
;     -- Total 0-input functions    ; 0       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 69      ;
; Total logic cells in carry chains ; 39      ;
; I/O pins                          ; 21      ;
; Maximum fan-out node              ; clk     ;
; Maximum fan-out                   ; 69      ;
; Total fan-out                     ; 935     ;
; Average fan-out                   ; 3.44    ;
+-----------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                      ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |i2c                       ; 251 (251)   ; 69           ; 0          ; 21   ; 0            ; 182 (182)    ; 31 (31)           ; 38 (38)          ; 39 (39)         ; |i2c                ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 69    ;
; Number of registers using Synchronous Clear  ; 3     ;
; Number of registers using Synchronous Load   ; 4     ;
; Number of registers using Asynchronous Clear ; 69    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 40    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; scl_xhdl1                              ; 2       ;
; en_xhdl3[1]                            ; 8       ;
; writeData_reg[2]                       ; 2       ;
; writeData_reg[0]                       ; 2       ;
; sda_buf                                ; 22      ;
; Total number of inverted registers = 5 ;         ;
+----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 12:1               ; 8 bits    ; 64 LEs        ; 0 LEs                ; 64 LEs                 ; Yes        ; |i2c|readData_reg[0]       ;
; 33:1               ; 2 bits    ; 44 LEs        ; 6 LEs                ; 38 LEs                 ; Yes        ; |i2c|main_state[0]         ;
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |i2c|seg_data_buf[0]       ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口實驗/i2c總線/i2c.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sat Feb 18 12:15:33 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off i2c -c i2c
Info: Found 2 design units, including 1 entities, in source file i2c.vhd
    Info: Found design unit 1: i2c-translated
    Info: Found entity 1: i2c
Info: Elaborating entity "i2c" for the top level hierarchy
Warning: VHDL Process Statement warning at i2c.vhd(145): signal or variable "addr" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "addr" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Duplicate registers merged to single register
    Info: Duplicate register "writeData_reg[4]" merged to single register "writeData_reg[7]"
    Info: Duplicate register "writeData_reg[5]" merged to single register "writeData_reg[7]"
    Info: Duplicate register "writeData_reg[6]" merged to single register "writeData_reg[7]"
Info: Duplicate registers merged to single register
    Info: Duplicate register "cnt_scan[0]" merged to single register "clk_div[0]"
Warning: Reduced register "writeData_reg[7]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "clk_div[1]" merged to single register "cnt_scan[1]"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "lowbit" stuck at GND
    Warning: Pin "seg_data[0]" stuck at VCC
Info: Registers with preset signals will power-up high
Info: Implemented 272 device resources after synthesis - the final resource count might be different
    Info: Implemented 8 input pins
    Info: Implemented 12 output pins
    Info: Implemented 1 bidirectional pins
    Info: Implemented 251 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
    Info: Processing ended: Sat Feb 18 12:15:46 2006
    Info: Elapsed time: 00:00:14