|-- a_csnbuffer:oflow_node
                |-- a_csnbuffer:result_node
           |-- addcore:adder[4]
                |-- a_csnbuffer:cout_node
                |-- a_csnbuffer:oflow_node
                |-- a_csnbuffer:result_node
           |-- altshift:carry_ext_latency_ffs
           |-- look_add:look_ahead_unit
                |-- look_add:$00004
                |-- look_add:$00006
           |-- altshift:oflow_ext_latency_ffs
           |-- altshift:result_ext_latency_ffs
      |-- lpm_constant:scdw


+---------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                             ;
+------------------------------+------------+------+------------------------------+
; Compilation Hierarchy Node   ; Macrocells ; Pins ; Full Hierarchy Name          ;
+------------------------------+------------+------+------------------------------+
; |lin                         ; 26         ; 13   ; |lin                         ;
;    |lpm_counter:count_rtl_0| ; 15         ; 0    ; |lin|lpm_counter:count_rtl_0 ;
+------------------------------+------------+------+------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in J:/產品系列/mcu+cpld+tcpip+ucos/程序/CPLD/驅動數碼管/復件 io卡verilog描述正規成功（修改鎖存器寫的方式---未加多串口部分，改用正規寫法讀寫可同時進行）/lin.map.eqn.


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                       ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+
; File Name                                                                                                                                                  ; Used in Netlist ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+
; J:/產品系列/mcu+cpld+tcpip+ucos/程序/CPLD/驅動數碼管/復件 io卡verilog描述正規成功（修改鎖存器寫的方式---未加多串口部分，改用正規寫法讀寫可同時進行）/lin.v ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf                                                                                                ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/lpm_constant.inc                                                                                               ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf                                                                                                ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/addcore.inc                                                                                                    ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/look_add.inc                                                                                                   ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/addcore.tdf                                                                                                    ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf                                                                                                ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/look_add.tdf                                                                                                   ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/altshift.tdf                                                                                                   ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/lpm_constant.tdf                                                                                               ; yes             ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 26                   ;
; Total registers      ; 15                   ;
; I/O pins             ; 13                   ;
; Maximum fan-out node ; clock                ;
; Maximum fan-out      ; 15                   ;
; Total fan-out        ; 158                  ;
; Average fan-out      ; 4.05                 ;
+----------------------+----------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Tue Jan 03 11:52:49 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off lin -c lin
Info: Using design file lin.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: lin
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=37) from the following logic: count[0]~0
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/look_add.tdf
    Info: Found entity 1: look_add
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/lpm_constant.tdf
    Info: Found entity 1: lpm_constant
Info: Issued messages during elaboration of megafunction lpm_counter:count_rtl_0|lpm_constant:scdw, which is child of megafunction lpm_counter:count_rtl_0
Info: Instantiated megafunction lpm_counter:count_rtl_0 with the following parameter:
    Info: Parameter LPM_WIDTH = 37
    Info: Parameter LPM_DIRECTION = UP
    Info: Parameter LPM_TYPE = LPM_COUNTER
Warning: Variable or input pin ag is defined but never used
Info: Ignored 15 buffer(s)
    Info: Ignored 15 SOFT buffer(s)
Warning: Output pins are stuck at VCC or GND
    Warning: Pin seg[7] stuck at VCC
    Warning: Pin seg[6] stuck at GND
    Warning: Pin seg[3] stuck at GND
    Warning: Pin seg[0] stuck at GND
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin clock to global clock signal
Info: Implemented 39 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 12 output pins
    Info: Implemented 26 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
    Info: Processing ended: Tue Jan 03 11:52:54 2006
    Info: Elapsed time: 00:00:04