/* This doesn't look like -*- C -*-, but it is! * * mips.def - SimpleScalar MIPS ISA (mips) machine definition * * This file is a part of the SimpleScalar tool suite written by * Todd M. Austin as a part of the Multiscalar Research Project. *   * The tool suite is currently maintained by Doug Burger and Todd M. Austin. *  * Copyright (C) 1994, 1995, 1996, 1997, 1998 by Todd M. Austin * * This source file is distributed "as is" in the hope that it will be * useful.  The tool set comes with no warranty, and no author or * distributor accepts any responsibility for the consequences of its * use.  *  * Everyone is granted permission to copy, modify and redistribute * this tool set under the following conditions: *  *    This source code is distributed for non-commercial use only.  *    Please contact the maintainer for restrictions applying to  *    commercial use. * *    Permission is granted to anyone to make or distribute copies *    of this source code, either as received or modified, in any *    medium, provided that all copyright notices, permission and *    nonwarranty notices are preserved, and that the distributor *    grants the recipient permission for further redistribution as *    permitted by this document. * *    Permission is granted to distribute this file in compiled *    or executable form under the same conditions that apply for *    source code, provided that either: * *    A. it is accompanied by the corresponding machine-readable *       source code, *    B. it is accompanied by a written offer, with no time limit, *       to give anyone a machine-readable copy of the corresponding *       source code in return for reimbursement of the cost of *       distribution.  This written offer must permit verbatim *       duplication by anyone, or *    C. it is distributed by someone who received only the *       executable form, and is accompanied by a copy of the *       written offer of source code that they received concurrently. * * In other words, you are welcome to use, share and improve this * source file.  You are forbidden to forbid anyone else to use, share * and improve what you give them. * * INTERNET: dburger@cs.wisc.edu * US Mail:  1210 W. Dayton Street, Madison, WI 53706 * * $Id: mips.def,v 1.1.1.1 2006/09/08 09:21:43 cvsuser Exp $ * * $Log: mips.def,v $ * Revision 1.1.1.1  2006/09/08 09:21:43  cvsuser * Godson-3 simulator * * Revision 1.1  2005/01/27 03:18:24  fxzhang * create godson2 cvs * * Revision 1.1.1.1  2004/12/05 14:36:32  fxzhang * initial import of ss-mips * * Revision 1.4  2004/11/18 04:30:32  fxzhang * dump simpoint enhancements * * Revision 1.3  2004/08/03 09:50:06  fxzhang * merge back changes on AMD64 * * Revision 1.3  2004/08/02 01:37:27  fxzhang * add readline support for dlite * fix sc implementation(eon runs now) * * Revision 1.2  2004/07/30 02:48:22  fxzhang * fix stat64/lstat64 * * Revision 1.2  2004/07/15 07:31:03  fxzhang * fix syscall on x86-64 * * Revision 1.1.1.1  2004/07/15 01:26:34  fxzhang * import * * Revision 1.2  2004/07/14 07:38:06  fxzhang * add bbtracker( simpoint ) support * * Revision 1.1.1.1  2004/07/10 16:46:48  fxzhang * initial * * Revision 1.1.1.1  2000/05/26 15:21:54  taustin * SimpleScalar Tool Set * * * Revision 1.9  1999/12/31 19:03:01  taustin * floating point divide-by-zero now allowed * * Revision 1.8  1999/12/13 19:00:48  taustin * cross endian execution support added * * Revision 1.7  1998/08/27 17:01:35  taustin * implemented host interface description in host.h * added target interface support * reorganized instruction semantics definitions; now using name-mangled *      macros, this approach is very portable (even works on MC VC++) and *      it allows C statements to portably implement instruction semantics * LWL/LWR/SWL/SWR semantics fixed in ss.def, these instruction now *       appear to work correctly on big- and little-endian machines, this *       fixes all previous problems with IJPEG failing during functional *       simulation * added support for fast shifts if host machine can successfully implement *       them, sysprobe tests if fast shifts work and then sets -DFAST_SRA and *       -DFAST_SRL accordingly; this also fixes shifts when the high order *       bit is set for some machines * * *//* This file defines all aspects of the SimpleScalar instruction set * architecture.  Each instruction set in the architecture has a DEFINST() * macro call included below.  The contents of a instruction definition are * as follows: * *   DEFINST(<enum>,			<opcode>, *	     <opname>,			<operands>, *	     <fu_req>,			<iflags>, *	     <output deps...>,		<input deps...>, *	     <expr>,			<primary_op>, *           <major_op>,		<extended_op>) * * Where: * *   <enum>	- is an enumerator that is returned when an instruction is *		  decoded by SS_OP_ENUM() *   <opcode>	- is the opcode of this instruction *   <opname>   - name of this instruction as a string, used by disassembler *   <operands>	- specified the instruction operand fields and their printed * 		  order for disassembly, used by disassembler, the recognized *		  operand field are (the instruction format is detailed in *		  the header file ss.h): *		    J - target field *		    j - PC relative target (offset + PC) *		    s - S register field *		    b - S register field (base register) *		    t - T register field *		    d - D register field *		    S - S register field (FP register) *		    T - T register field (FP register) *		    D - D register field (FP register) *		    o - load address offset (offset) *		    i - signed immediate field value *		    u - unsigned immediate field value *		    U - upper immediate field value *		    H - shift amount immediate field value *		    B - break code * *   <fu_req>	- functional unit requirements for this instruction *   <iflags>	- instruction flags, accessible via the SS_OP_FLAGS() *		  macro, flags are defined with F_* prefix in ss.h *   <output deps...> *		- a list of up to two output dependency designators, the *		  following designators are recognized (place an DNA in any *		  unused fields: *		    DGPR(N)   - general purpose register N *		    DGPR_D(N) - double word general purpose register N *		    DCGPR(N)  - general purpose register conditional on *			        pre/post- increment/decrement mode *		    DFPR_L(N) - floating-point register N, as word *		    DFPR_F(N) - floating-point reg N, as single-prec float *		    DFPR_D(N) - floating-point reg N, as double-prec double *		    DHI	      - HI result register *		    DLO	      - LO result register *		    DFCC      - floating point condition codes *		    DCPC      - current PC *		    DNPC      - next PC *		    DNA	      - no dependence * *   <input deps...> *		- a list of up to three input dependency designators, the *		  designators are defined above (place an DNA in any unused *		  fields. * *   <expr>	- a C expression that implements the instruction being * 		  defined, the expression must modify all architected state *		  affected by the instruction's execution, by default, the *		  next PC (NPC) value defaults to the current PC (CPC) plus *		  SS_INST_SIZE, as a result, only taken branches need to set *		  NPC * *		  The following predefined macros are available for use in *		  DEFINST() instruction expressions to access the value of *		  instruction operand/opcode field values: * *		    RS	    - RS register field value *		    RT	    - RT register field value *		    RD	    - RD register field value *		    FS	    - RS register field value *		    FT	    - RT register field value *		    FD	    - RD register field value *		    BS	    - RS register field value *		    TARG    - jump target field value *		    OFS	    - signed offset field value *		    IMM	    - signed offset field value *		    UIMM    - unsigned offset field value *		    SHAMT   - shift amount field value *		    BCODE   - break code field value * *		  To facilitate the construction of performance simulators *		  (which may want to specialize their architected state *		  storage format), all architected register and memory state *		  is accessed through the following macros: * *		    GPR(N)         - read general purpose register N *		    SET_GPR(N,E)   - write general purpose register N with E *		    GPR_D(N)       - read double word general purpose reg N *		    SET_GPR_D(N,E) - write double word gen purpose reg N w/ E *		    FPR_L(N)       - read floating-point register N, as word *		    SET_FPR_L(N,E) - floating-point reg N, as word, with E *		    FPR_F(N)       - read FP reg N, as single-prec float *		    SET_FPR_F(N,E) - write FP reg N, as single-prec float w/ E *		    FPR_D(N)       - read FP reg N, as double-prec double *		    SET_FPR_D(N,E) - write FP reg N, as double-prec double w/E *		    HI	           - read HI result register *		    SET_HI(E)      - write HI result register with E *		    LO	           - read LO result register *		    SET_LO(E)      - write LO result register with E *		    FCC	           - read floating point condition codes *		    SET_FCC(E)     - write floating point condition codes w/ E *		    CPC	           - read current PC register *		    NPC	           - read next PC register *		    SET_NPC(E)     - write next PC register with E *		    TPC	           - read target PC register *		    SET_TPC(E)     - write target PC register with E * *		    READ_SIGNED_BYTE(A)   - read signed byte from address A *		    READ_UNSIGNED_BYTE(A) - read unsigned byte from address A *		    READ_SIGNED_HALF(A)   - read signed half from address A *		    READ_UNSIGNED_HALF(A) - read unsigned half from address A *		    READ_WORD(A)          - read word from address A *		    WRITE_BYTE(E,A)       - write byte value E to address A *		    WRITE_HALF(E,A)       - write half value E to address A *		    WRITE_WORD(E,A)       - write word value E to address A * *		  Finally, the following helper functions are available to *		  assist in the construction of instruction expressions: * *		    INC_DEC(E,N,S) - execute E and update N as per pre/post- *				     incr/decr addressing sementics for an *				     access of S bytes *		    OVER(X,Y)      - check for overflow for X+Y, both signed *		    UNDER(X,Y)	   - check for umderflow for X-Y, both signed *		    DIV0(N)	   - check for divide by zero, N is denom *		    INTALIGN(N)    - check double word int reg N alignment *		    FPALIGN(N)	   - check double word FP reg N alignment *		    TALIGN(T)	   - check jump target T alignment */DEFLINK(SPECIAL_INST, 0x00, "special", 0, 0x3f)DEFLINK(REGIMM_INST , 0x01, "regimm", 16, 0x1f)/*DEFLINK(COP0_INST   , 0x10, "cop0",   21, 0x1f)*/DEFLINK(COP1_INST   , 0x11, "cop1",   21, 0x1f)/*DEFLINK(CACHE_INST  , 0x2f, "cache",  16, 0x1f) *//* first level opcode instructions */#define JUMP_IMPL							\  {									\    SET_TPC((CPC & 036000000000) | (TARG << 2));			\    is_jump = 1;							\  }DEFINST(JUMP,			0x02,	"j",			"J",	NA, 			F_CTRL|F_UNCOND|F_DIRJMP,	DNA, DNA, 		DNA, DNA, DNA)#define JAL_IMPL							\  {									\    SET_TPC((CPC & 036000000000) | (TARG << 2));			\    SET_GPR(31, CPC + 8);						\    is_jump = 1;							\  }DEFINST(JAL,			0x03,	"jal",			"J",	IntALU,			F_CTRL|F_UNCOND|F_DIRJMP|F_CALL,	DGPR(31), DNA,	 	DNA, DNA, DNA)#define BEQ_IMPL							\  {									\    SET_TPC(CPC + 4 + (OFS << 2));					\    if (GPR(RS) == GPR(RT))						\    {									\      is_jump = 1;							\    }									\  }DEFINST(BEQ,			0x04,	"beq",			"s,t,j",	IntALU,			F_CTRL|F_COND|F_DIRJMP,	DNA, DNA,		DGPR(RS), DGPR(RT), DNA)#define BNE_IMPL							\  {									\    SET_TPC(CPC + 4 + (OFS << 2));					\    if (GPR(RS) != GPR(RT))						\    {									\      is_jump = 1;							\    }									\  }DEFINST(BNE,			0x05,	"bne",			"s,t,j",	IntALU,			F_CTRL|F_COND|F_DIRJMP,	DNA, DNA,		DGPR(RS), DGPR(RT), DNA)#define BLEZ_IMPL							\  {									\    SET_TPC(CPC + 4 + (OFS << 2));					\    if (GPR(RS) <= 0)							\    {									\      is_jump = 1;							\    }									\  }DEFINST(BLEZ,			0x06,	"blez",			"s,j",	IntALU,			F_CTRL|F_COND|F_DIRJMP,	DNA, DNA,		DGPR(RS), DNA, DNA)#define BGTZ_IMPL							\  {									\    SET_TPC(CPC + 4 + (OFS << 2));					\    if (GPR(RS) > 0)							\    {									\      is_jump = 1;							\    }									\  }DEFINST(BGTZ,			0x07,	"bgtz",			"s,j",	IntALU,			F_CTRL|F_COND|F_DIRJMP,	DNA, DNA,		DGPR(RS), DNA, DNA)#define ADDI_IMPL							\  {									\    if (OVER(GPR(RS), IMM))						\      DECLARE_FAULT(md_fault_overflow);					\									\    SET_GPR(RT, GPR(RS) + IMM);						\  }DEFINST(ADDI,			0x08,	"addi",			"t,s,i",	IntALU,			F_ICOMP|F_IMM,	DGPR(RT), DNA, 		DGPR(RS), DNA, DNA)#define ADDIU_IMPL							\  {									\    SET_GPR(RT, GPR(RS) + IMM);						\  }DEFINST(ADDIU,			0x09,	"addiu",		"t,s,i",	IntALU,			F_ICOMP|F_IMM,	DGPR(RT), DNA, 		DGPR(RS), DNA, DNA)#define SLTI_IMPL							\  {									\    if (GPR(RS) < IMM)							\      SET_GPR(RT, 1);							\    else								\      SET_GPR(RT, 0);							\  }DEFINST(SLTI, 			0x0a,	"slti",			"t,s,i",	IntALU,			F_ICOMP|F_IMM,	DGPR(RT), DNA, 		DGPR(RS), DNA, DNA)#define SLTIU_IMPL							\  {									\    if ((unsigned)GPR(RS) < (unsigned)IMM)				\      SET_GPR(RT, 1);							\    else								\      SET_GPR(RT, 0);							\  }DEFINST(SLTIU,			0x0b,	"sltiu",		"t,s,i",	IntALU,			F_ICOMP|F_IMM,	DGPR(RT), DNA, 		DGPR(RS), DNA, DNA)#define ANDI_IMPL							\  {									\    SET_GPR(RT, GPR(RS) & UIMM);					\  }DEFINST(ANDI,			0x0c,	"andi",			"t,s,u",	IntALU,			F_ICOMP|F_IMM,	DGPR(RT), DNA,	 	DGPR(RS), DNA, DNA)#define ORI_IMPL							\  {									\    SET_GPR(RT, GPR(RS) | UIMM);					\  }DEFINST(ORI, 			0x0d,	"ori",			"t,s,u",	IntALU,			F_ICOMP|F_IMM,	DGPR(RT), DNA, 		DGPR(RS), DNA, DNA)#define XORI_IMPL							\  {									\    SET_GPR(RT, GPR(RS) ^ UIMM);					\  }DEFINST(XORI, 			0x0e,	"xori",			"t,s,u",	IntALU,			F_ICOMP|F_IMM,	DGPR(RT), DNA, 		DGPR(RS), DNA, DNA)#define LUI_IMPL							\  {									\    SET_GPR(RT, UIMM << 16);						\  }DEFINST(LUI, 			0x0f,	"lui",			"t,U",	IntALU,			F_ICOMP,	DGPR(RT), DNA, 		DNA, DNA, DNA)#define BEQL_IMPL							\  {									\    SET_TPC(CPC + 4 + (OFS << 2));					\    if (GPR(RS) == GPR(RT))						\    {									\      is_jump = 1;							\    }else is_annulled = 1; 						\}DEFINST(BEQL,			0x14,	"beql",			"s,t,j",	IntALU,			F_CTRL|F_COND|F_DIRJMP,	DNA, DNA,		DGPR(RS), DGPR(RT), DNA)#define BNEL_IMPL							\  {									\    SET_TPC(CPC + 4 + (OFS << 2));					\    if (GPR(RS) != GPR(RT))						\    {									\      is_jump = 1;							\    }else is_annulled = 1; 						\  }DEFINST(BNEL,			0x15,	"bnel",			"s,t,j",	IntALU,			F_CTRL|F_COND|F_DIRJMP,	DNA, DNA,		DGPR(RS), DGPR(RT), DNA)#define BLEZL_IMPL							\  {									\    SET_TPC(CPC + 4 + (OFS << 2));					\    if (GPR(RS) <= 0)							\    {									\      is_jump = 1;							\    }else is_annulled = 1; 						\  }DEFINST(BLEZL,			0x16,	"blezl",		"s,j",	IntALU,			F_CTRL|F_COND|F_DIRJMP,	DNA, DNA,		DGPR(RS), DNA, DNA)#define BGTZL_IMPL							\  {									\    SET_TPC(CPC + 4 + (OFS << 2));					\    if (GPR(RS) > 0)							\    {									\      is_jump = 1;							\    }else is_annulled = 1; 						\  }DEFINST(BGTZL,			0x17,	"bgtzl",		"s,j",	IntALU,			F_CTRL|F_COND|F_DIRJMP,	DNA, DNA,		DGPR(RS), DNA, DNA)/* * load/store operations * * NOTE: the out-of-order issue simulator(s) require that load and store * address computation input dependencies be placed in slots 1 and 2 of * the input dependency list slot 0 is reserved for the input dependency * of store values for store instructions */#define LB_IMPL								\  {									\    sbyte_t _result;							\    enum md_fault_type _fault;						\									\    _result = READ_BYTE(GPR(BS) + OFS, _fault);				\    if (_fault != md_fault_none)					\      DECLARE_FAULT(_fault);						\    SET_GPR(RT, (word_t)(sword_t)_result);				\  }DEFINST(LB,			0x20,	"lb",			"t,o(b)",	RdPort,			F_MEM|F_LOAD|F_DISP,	DGPR(RT), DNA,		DNA, DGPR(BS), DNA)#define LH_IMPL								\  {									\    shalf_t _result;							\    enum md_fault_type _fault;						\									\    _result = READ_HALF(GPR(BS) + OFS, _fault);				\    if (_fault != md_fault_none)					\      DECLARE_FAULT(_fault);						\    SET_GPR(RT, (word_t)(sword_t)_result);				\  }DEFINST(LH, 			0x21,	"lh",			"t,o(b)",	RdPort,			F_MEM|F_LOAD|F_DISP,	DGPR(RT), DNA,		DNA, DGPR(BS), DNA)#define LW_IMPL								\  {									\    word_t _result;							\    enum md_fault_type _fault;						\									\    _result = READ_WORD(GPR(BS) + OFS, _fault);				\    if (_fault != md_fault_none)					\      DECLARE_FAULT(_fault);						\    SET_GPR(RT, _result);						\  }DEFINST(LW,			0x23,	"lw", 			"t,o(b)",	RdPort,			F_MEM|F_LOAD|F_DISP,	DGPR(RT), DNA,		DNA, DGPR(BS), DNA)#define LBU_IMPL							\  {									\    byte_t _result;							\    enum md_fault_type _fault;						\									\    _result = READ_BYTE(GPR(BS) + OFS, _fault);				\    if (_fault != md_fault_none)					\      DECLARE_FAULT(_fault);						\    SET_GPR(RT, (word_t)_result);					\  }DEFINST(LBU, 			0x24, 	"lbu", 			"t,o(b)",	RdPort, 		F_MEM|F_LOAD|F_DISP,	DGPR(RT), DNA,		DNA, DGPR(BS), DNA)#define LHU_IMPL							\  {									\    half_t _result;							\    enum md_fault_type _fault;						\									\    _result = READ_HALF(GPR(BS) + OFS, _fault);				\    if (_fault != md_fault_none)					\      DECLARE_FAULT(_fault);						\    SET_GPR(RT, (word_t)_result);					\  }DEFINST(LHU, 			0x25, 	"lhu", 			"t,o(b)",	RdPort, 		F_MEM|F_LOAD|F_DISP,	DGPR(RT), DNA,		DNA, DGPR(BS), DNA)#define LWC1_IMPL							\  {									\    word_t _result;							\    enum md_fault_type _fault;						\									\    _result = READ_WORD(GPR(BS) + OFS, _fault);				\    if (_fault != md_fault_none)					\      DECLARE_FAULT(_fault);						\    SET_FPR_L(FT, _result);						\  }DEFINST(LWC1, 			0x31,	"lwc1",			"T,o(b)",	RdPort,			F_MEM|F_LOAD|F_DISP,	DFPR_L(FT), DNA,	DNA, DGPR(BS), DNA)#define LDC1_IMPL							\  {									\    word_t _result_hi, _result_lo;					\    enum md_fault_type _fault;						\