/* romInit.s - ARM Integrator ROM initialization module *//* Copyright 1999-2001 ARM Limited *//* Copyright 1999-2001 Wind River Systems, Inc. *//*modification history--------------------01m,25jan02,m_h  sdata needs "_" for bootrom_res01l,09oct01,jpd  added clock speed setting for 946ES.01k,03oct01,jpd  tidied slightly.01j,28sep01,pr   added support for ARM946ES.01i,04jun01,rec  memory clock rate changes for 740t01h,21feb01,h_k  added support for ARM966ES and ARM966ES_T.01g,20nov00,jpd  change speeds on 920T and add conditional early		 enabling of I-cache on 920T.01f,18sep00,rec  Add delay during power up01e,23feb00,jpd  comments changes.01d,22feb00,jpd  changed copyright string.01c,20jan00,jpd  added support for ARM720T/ARM920T.01b,13jan00,pr	 added support for ARM740T.01a,30nov99,ajb  created, based on PID version 01i.*//*DESCRIPTIONThis module contains the entry code for VxWorks images that startrunning from ROM, such as 'bootrom' and 'vxWorks_rom'.  The entrypoint, romInit(), is the first code executed on power-up.  It performsthe minimal setup needed to call the generic C routine romStart() withparameter BOOT_COLD.romInit() masks interrupts in the processor and the interruptcontroller and sets the initial stack pointer (to STACK_ADRS which isdefined in configAll.h).  Other hardware and device initialisation isperformed later in the sysHwInit routine in sysLib.c.The routine sysToMonitor() jumps to a location after the beginning ofromInit, (defined by ROM_WARM_ADRS) to perform a "warm boot".  Thisentry point allows a parameter to be passed to romStart().The routines in this module don't use the "C" frame pointer %r11@ ! orestablish a stack frame.SEE ALSO:.I "ARM Architecture Reference Manual,".I "ARM 7TDMI Data Sheet,". "ARM 720T Data Sheet,".I "ARM 740T Data Sheet,".I "ARM 920T Technical Reference Manual",.I "ARM 940T Technical Reference Manual",.I "ARM 946E-S Technical Reference Manual",.I "ARM 966E-S Technical Reference Manual",.I "ARM Reference Peripherals Specification,".I "ARM Integrator/AP User Guide",.I "ARM Integrator/CM7TDMI User Guide",.I "ARM Integrator/CM720T User Guide",.I "ARM Integrator/CM740T User Guide",.I "ARM Integrator/CM920T User Guide",.I "ARM Integrator/CM940T User Guide",.I "ARM Integrator/CM946E User Guide",.I "ARM Integrator/CM9x6ES Datasheet".*/#define	_ASMLANGUAGE#include "vxWorks.h"#include "sysLib.h"#include "asm.h"#include "regs.h"	#include "config.h"#include "s3c2410.h"#include "arch/arm/mmuArmLib.h"#include "memcfg.h"     /*SDRAM config register*/	.data        .globl   VAR(copyright_wind_river)        .long    VAR(copyright_wind_river)/* internals */	.globl	FUNC(romInit)		/* start of system code */	.globl	VAR(sdata)		/* start of data */        .globl  _sdata	.globl	VAR(integratorMemSize)	/* actual memory size */	.globl  FUNC(DisableIcache)/* externals */	.extern	FUNC(romStart)	/* system initialization routine */_sdata:VAR_LABEL(sdata)	.asciz	"start of data"	.balign	4/* variables */	.dataVAR_LABEL(integratorMemSize)	.long	0	.text	.balign 4/********************************************************************************* romInit - entry point for VxWorks in ROM** romInit*     (*     int startType	/@ only used by 2nd entry point @/*     )* INTERNAL* sysToMonitor examines the ROM for the first instruction and the string* "Copy" in the third word so if this changes, sysToMonitor must be updated.*/_ARM_FUNCTION(romInit)_romInit:        B       cold        B       _romUndef        B       _romSwi        B       _romPrefetch        B       _romDataAbort        B       _romReserved              /* _romReserved */        B       _romIRQ        B       _romFIQ                  /* _romFIQ     */cold:	MOV	r0, #BOOT_COLD	/* fall through to warm boot entry */warm:	B	start	/* copyright notice appears at beginning of ROM (in TEXT segment) */	.ascii   "Copyright 1999-2001 ARM Limited"	.ascii   "\nCopyright 1999-2001 Wind River Systems, Inc."	.balign 4start:        ldr    r2,=0x40000000	/*internal sram,just store r0*/	str    r0,[r2]        /*	 * There have been reports of problems with certain boards and	 * certain power supplies not coming up after a power-on reset,	 * and adding a delay at the start of romInit appears to help	 * with this.	 */	TEQS	r0, #BOOT_COLD	MOVEQ	r1, #INTEGRATOR_DELAY_VALUE	MOVNE	r1, #1delay_loop:        SUBS	r1, r1, #1	BNE	delay_loop		/* Setup MMU Control Register */	MOV	r1, #MMU_INIT_VALUE		/* Defined in mmuArmLib.h */	ORR	r1, r1, #MMUCR_I_ENABLE		/* enable Icache*/	MCR	CP_MMU, 0, r1, c1, c0, 0	/* Write to MMU CR */	MOV	r1, #0				/* data SBZ */	MCR	CP_MMU, 0, r1, c7, c10, 4	/* drain write-buffer */	MCR	CP_MMU, 0, r1, c7, c7, 0	/* R1 = 0 from above, data SBZ*/		/*	 * Set Process ID Register to zero, this effectively disables	 * the process ID remapping feature.	 */	MOV	r1, #0	MCR	CP_MMU, 0, r1, c13, c0, 0	        /* disable interrupts in CPU and switch to SVC32 mode */	MRS	r1, cpsr	BIC	r1, r1, #MASK_MODE	ORR	r1, r1, #MODE_SVC32 | I_BIT | F_BIT	MSR	cpsr, r1	        ldr   r0,L$_INTMSK        /*all interrupt disable(if  r1=0x00000000 all interrupt service)*/    	ldr   r1,=0xffffffff    	str   r1,[r0]	ldr   r0,L$_INTSUBMSK     /*all subinterrupt disable*/    	ldr   r1,=0x7ff            /*(only ten subinterrupt are valid in 2410 from low end*/    	str   r1,[r0]              /*so r1= 0x7ff)*/    	    	/*	 * Jump to the normal (higher) ROM Position. After a reset, the	 * ROM is mapped into memory from* location zero upwards as well	 * as in its normal position at This code could be executing in	 * the lower position. We wish to be executing the code, still	 * in ROM, but in its normal (higher) position before we remap	 * the machine so that the ROM is no longer dual-mapped from zero	 * upwards, but so that RAM appears from 0 upwards.	 */	LDR	pc, L$_HiPosnHiPosn:		ldr   r0,L$_WTCON         /*disable watch dog*/    	ldr   r1,=0x0    	str   r1,[r0]    	    	/*turn on the led,and make it glitter*/    	ldr   r0,=GPBCON        /*config the I/O of port F*/    	ldr   r1,=0x55555555    	str   r1,[r0]		ldr   r0,=GPBUP	ldr   r1,=0xffffffff	ldr   r1,[r0]		ldr   r0,=0xffffffff	ldr   r1,=GPBDAT	str   r0,[r1]		ldr r0,=LOCKTIME        /* To reduce PLL lock time, adjust the LOCKTIME register.*/
        ldr r1,=0xffffff
        str r1,[r0]        	ldr   r0,L$_MPLLCON	/* config PLL */   	ldr   r1,L$_FCLKCFG	str   r1,[r0]   		ldr r0,=CLKDIVN         /* colck divider */ 
        ldr r1,=DIVCFG
        str r1,[r0]                  mrc CP_MMU,0,r0,c1,c0,0    /* clock mode */
        orr r0,r0,#R1_nF | R1_iA        mcr CP_MMU,0,r0,c1,c0,0         		/*SDRAM init,BANKx init*/	/*only 13 registers need to be init*/	ldr   r0 ,L$_valSMRDATA	   /*SDRAM config value*/	ldr   r1 ,L$_valSMRDATA + 0x04	ldr   r2 ,L$_valSMRDATA + 0x08	ldr   r3 ,L$_valSMRDATA + 0x0C	ldr   r4 ,L$_valSMRDATA + 0x10	ldr   r5 ,L$_valSMRDATA + 0x14	ldr   r6 ,L$_valSMRDATA + 0x18	ldr   r7 ,L$_valSMRDATA + 0x1C	ldr   r8 ,L$_valSMRDATA + 0x20	ldr   r9 ,L$_valSMRDATA + 0x24	ldr   r10,L$_valSMRDATA + 0x28	ldr   r11,L$_valSMRDATA + 0x2C	ldr   r12,L$_valSMRDATA + 0x30    	ldr   r13,L$_BWSCON    	stmia r13,{r0-r12}         	   	/*ok SDRAM and BANKx are also initialised*/   		/*	*  sys timer and aux timer init*/			ldr	r0,=TCFG1	  /* timer3 timer4 divider value = 2 */ 	ldr	r1,=0xfff00fff	str	r1,[r0]		ldr	r0,=TCFG0    /* timer3 timer4 prescaler = 68 */	ldr	r1,=0x00004400	str	r1,[r0]		ldr	r0,=TCNTB4  /*TCNTB4*/	ldr	r1,=20000	str	r1,[r0]		ldr	r0,=TCON  /*TCON*/	ldr	r1,=0x600000	str	r1,[r0]		ldr	r0,=TCON  /*TCON*/	ldr	r1,=0x500000	str	r1,[r0]		ldr	r0,=TCNTB3  /*TCNTB3*/	ldr	r1,=1000	str	r1,[r0]		ldr	r0,=TCON  /*TCON*/	ldr	r1,=0x5A0000	str	r1,[r0]		ldr	r0,=TCON  /*TCON*/	ldr	r1,=0x590000	str	r1,[r0]		/*The interrupt and sub interrupt,watchdog are disable,sdram and other bankx are	also init at this point.*/ 	/*add end*//***************************************************************************************/	ldr    r5, =0x40000000	ldr    r0, [r5]        /* restore starttype to r0 from r13 */	LDR    sp, L$_STACK_ADDR	MOV    fp, #0			/* zero frame pointer */	/* jump to C entry point in ROM: routine - entry point + ROM base */	LDR	pc, L$_rStrtInRom/******************************************************************************//*;; ====================================================================;; Name:	ROM_FIQ;; Function:	This routine helps to pass control to proper FIQ handler;;		once a FIQ interrupt occurs;; ====================================================================	*/_ARM_FUNCTION(romFIQ)_romFIQ:	sub	sp, sp, #4	stmfd	sp!, {r0}	ldr	r0, L$_promFIQ         	ldr	r0, [r0]	str	r0, [sp, #4]	ldmfd	sp!, {r0, pc}/*	;; ====================================================================;; Name:	ROM_IRQ;; Function:	This routine helps to pass control to proper IRQ handler;;		once an IRQ interrupt occurs;; ====================================================================	*/_ARM_FUNCTION(romIRQ)_romIRQ:    	sub	sp, sp, #4		stmfd	sp!, {r0}	ldr	r0, L$_promIRQ    /*L$_promIRQ     */	ldr	r0, [r0]	str	r0, [sp, #4]    	ldmfd	sp!, {r0, pc}/*;; ====================================================================;; Name:	ROM_RESERVED;; Function:	This routine helps to pass control to proper RESERVED;;		handler once the RESERVED exception occurs;; ====================================================================	*/_ARM_FUNCTION(romReserved)_romReserved:	sub	sp, sp, #4	stmfd	sp!, {r0}	ldr	r0, L$_promReserved         	ldr	r0, [r0]	str	r0, [sp, #4]        	ldmfd	sp!, {r0, pc}/*		;; ====================================================================;; Name:	ROM_DATAABORT;; Function:	This routine helps to pass control to proper DATAABORT;;		handler once the DATAABORT exception occurs;; ====================================================================	*/_ARM_FUNCTION(romDataAbort)_romDataAbort:	sub	sp, sp, #4	stmfd	sp!, {r0}	ldr	r0, L$_promDataAbort   	ldr	r0, [r0]	str	r0, [sp, #4]	ldmfd	sp!, {r0, pc}/*;; ====================================================================;; Name:	ROM_PREFETCH;; Function:	This routine helps to pass control to proper PREFETCH;;		handler once the PREFETCH exception occurs;; ====================================================================	*/_ARM_FUNCTION(romPrefetch)_romPrefetch:	sub	sp, sp, #4	stmfd	sp!, {r0}	ldr	r0, L$_promPrefetch    	ldr	r0, [r0]          	str	r0, [sp, #4]	ldmfd	sp!, {r0, pc}/*;; ====================================================================;; Name:	ROM_SWI;; Function:	This routine helps to pass control to proper SWI handler;;		once SWI is called by program;; ====================================================================	*/_ARM_FUNCTION(romSwi)_romSwi:	sub	sp, sp, #4	stmfd	sp!, {r0}	ldr	r0, L$_promSwi     	ldr	r0, [r0]	str	r0, [sp, #4]	ldmfd	sp!, {r0, pc}/*	;; ====================================================================;; Name:	ROM_UNDEFINED;; Function:	This routine helps to pass control to proper UNDEFINED;;		handler once the UNDEFINED exception occurs;; ====================================================================	*/_ARM_FUNCTION(romUndef)_romUndef:	sub	sp, sp, #4	stmfd	sp!, {r0}	ldr	r0, L$_promUndef               	ldr	r0, [r0]            	str	r0, [sp, #4]	ldmfd	sp!, {r0, pc}	@_ARM_FUNCTION(DisableIcache)	@_DisableIcache:@        mrc CP_MMU,0,r1,c1,c0,0    
@        and r1, r1, #~MMUCR_I_ENABLE@        mcr CP_MMU,0,r1,c1,c0,0    @        mov pc, r14 	/* * PC-relative-addressable pointers - LDR Rn,=sym is broken * note "_" after "$" to stop preprocessor performing substitution */	.balign	4L$_HiPosn:	.long	ROM_TEXT_ADRS + HiPosn - FUNC(romInit)L$_rStrtInRom:	.long	ROM_TEXT_ADRS + FUNC(romStart) - FUNC(romInit)L$_STACK_ADDR:	.long	STACK_ADRSL$_memSize:	.long	VAR(integratorMemSize)/*S3C2410X internal register ,add by yang tian chi,define in 2410addr.h*/L$_WTCON:	.long   WTCON		/*watchdog control */L$_INTMSK:	.long   INTMSK		/*int mask register*/L$_INTSUBMSK:	.long	INTSUBMSK	/*sub interrupt mask register*/L$_GPBCON:	.long	GPBCON		/*port B config register*/L$_GPBDAT:	.long	GPBDAT		/*port B data register*/L$_GPBUP:        .long   GPBUP		L$_BWSCON:	.long	BWSCON		/*mem cfg register base address*/L$_FCLKCFG:	.long	FCLKCFG		/*FCLK config value*/L$_MPLLCON:	.long	MPLLCON	/*PLL config parameter register*/L$_valSMRDATA:	.long	valBWSCON	.long	valBANKCON0	.long	valBANKCON1	.long	valBANKCON2	.long	valBANKCON3	.long	valBANKCON4	.long	valBANKCON5	.long	valBANKCON6	.long	valBANKCON7	.long	valREFRESH	.long	valBANKSIZE	.long	valMRSBR6	.long	valMRSBR7L$_RomCopySize:    .long    L$_RomCopySize - FUNC(romInit)    L$_promUndef:    .long     S3C_EXC_BASE  /* undef handler */L$_promSwi:    .long     S3C_EXC_BASE + 0x04  /* swi handler */L$_promPrefetch:    .long     S3C_EXC_BASE + 0x08  L$_promDataAbort:    .long     S3C_EXC_BASE + 0x0c L$_promReserved:    .long     S3C_EXC_BASE + 0x10L$_promIRQ:    .long     S3C_EXC_BASE + 0x14  /* IRQ */L$_promFIQ:    .long     S3C_EXC_BASE + 0x18  #if defined(CPU_940T) || defined (CPU_940T_T)L$_sysCacheUncachedAdrs:	.long	SYS_CACHE_UNCACHED_ADRSL$_SDRAM_TOP_ADDR:	.long	SDRAM_TOP_ADDR#endif /* defined(CPU_940T, CPU_940T_T) */