// ----------------------------------------------------------------------------//          ATMEL Microcontroller Software Support  -  ROUSSET  -// ----------------------------------------------------------------------------//  The software is delivered "AS IS" without warranty or condition of any//  kind, either express, implied or statutory. This includes without//  limitation any warranty or condition with respect to merchantability or//  fitness for any particular purpose, or against the infringements of//  intellectual property rights of others.// ----------------------------------------------------------------------------// File Name           : AT91C221.h// Object              : AT91C221 definitions// Generated           : AT91 SW Application Group  10/20/2004 (11:45:58)// // CVS Reference       : /AT91C221.pl/0/dummy timestamp//// CVS Reference       : /SYS_AT91C221.pl/0/dummy timestamp//// CVS Reference       : /AIC_1246F.pl/1.4/Mon Nov 04 17:51:00 2002//// CVS Reference       : /PIO_6033B.pl/0/dummy timestamp//// CVS Reference       : /TC_6033B.pl/0/dummy timestamp//// CVS Reference       : /PDC_1363D.pl/1.3/Wed Oct 23 14:49:48 2002//// CVS Reference       : /US_6033B.pl/0/dummy timestamp//// CVS Reference       : /SPI_6033B.pl/0/dummy timestamp//// CVS Reference       : /EMAC_6033B.pl/0/dummy timestamp//// CVS Reference       : /SDRC_6033B.pl/0/dummy timestamp//// CVS Reference       : /SMC_6033B.pl/0/dummy timestamp//// CVS Reference       : /SYSC_6033B.pl/0/dummy timestamp//// ----------------------------------------------------------------------------#ifndef AT91C221_H#define AT91C221_Htypedef volatile unsigned int AT91_REG;// Hardware register definition// *****************************************************************************//              SOFTWARE API DEFINITION  FOR System Peripherals// *****************************************************************************typedef struct _AT91S_SYS {	AT91_REG	 SYSC_MD; 	// Mode Register	AT91_REG	 SYSC_ID; 	// ID Register	AT91_REG	 Reserved0[1]; 	// 	AT91_REG	 SYSC_CLKF; 	// Clock Status Register	AT91_REG	 Reserved1[4092]; 	// 	AT91_REG	 EBI_SMC2_CSR[4]; 	// SMC2 Chip Select Register	AT91_REG	 Reserved2[5]; 	// 	AT91_REG	 EBI_SMC2_MCR; 	// SMC2 Memory Control Register	AT91_REG	 Reserved3[4086]; 	// 	AT91_REG	 EBI_SDRC_MR; 	// SDRAM Controller Mode Register	AT91_REG	 EBI_SDRC_TR; 	// SDRAM Controller Refresh Timer Register	AT91_REG	 EBI_SDRC_CR; 	// SDRAM Controller Configuration Register	AT91_REG	 EBI_SDRC_16BITR; 	// SDRAM 16-bit Configuration Register	AT91_REG	 EBI_SDRC_ADDR; 	// SDRAM Base Address for SDCS	AT91_REG	 Reserved4[4091]; 	// 	AT91_REG	 PIOA_PER; 	// PIO Enable Register	AT91_REG	 PIOA_PDR; 	// PIO Disable Register	AT91_REG	 PIOA_PSR; 	// PIO Status Register	AT91_REG	 Reserved5[1]; 	// 	AT91_REG	 PIOA_OER; 	// Output Enable Register	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr	AT91_REG	 PIOA_OSR; 	// Output Status Register	AT91_REG	 Reserved6[5]; 	// 	AT91_REG	 PIOA_SODR; 	// Set Output Data Register	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register	AT91_REG	 Reserved7[4076]; 	// 	AT91_REG	 PIOB_PER; 	// PIO Enable Register	AT91_REG	 PIOB_PDR; 	// PIO Disable Register	AT91_REG	 PIOB_PSR; 	// PIO Status Register	AT91_REG	 Reserved8[1]; 	// 	AT91_REG	 PIOB_OER; 	// Output Enable Register	AT91_REG	 PIOB_ODR; 	// Output Disable Registerr	AT91_REG	 PIOB_OSR; 	// Output Status Register	AT91_REG	 Reserved9[5]; 	// 	AT91_REG	 PIOB_SODR; 	// Set Output Data Register	AT91_REG	 PIOB_CODR; 	// Clear Output Data Register	AT91_REG	 PIOB_ODSR; 	// Output Data Status Register	AT91_REG	 PIOB_PDSR; 	// Pin Data Status Register	AT91_REG	 PIOB_IER; 	// Interrupt Enable Register	AT91_REG	 PIOB_IDR; 	// Interrupt Disable Register	AT91_REG	 PIOB_IMR; 	// Interrupt Mask Register	AT91_REG	 PIOB_ISR; 	// Interrupt Status Register	AT91_REG	 Reserved10[32748]; 	// 	AT91_REG	 AIC_SMR[32]; 	// Source Mode egister	AT91_REG	 AIC_SVR[32]; 	// Source Vector egister	AT91_REG	 AIC_IVR; 	// IRQ Vector Register	AT91_REG	 AIC_FVR; 	// FIQ Vector Register	AT91_REG	 AIC_ISR; 	// Interrupt Status Register	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register	AT91_REG	 Reserved11[2]; 	// 	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command egister	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register	AT91_REG	 AIC_SPU; 	// Spurious Vector Register} AT91S_SYS, *AT91PS_SYS;// *****************************************************************************//              SOFTWARE API DEFINITION  FOR Static Memory Controller 2 Interface// *****************************************************************************typedef struct _AT91S_SMC2 {	AT91_REG	 SMC2_CSR[4]; 	// SMC2 Chip Select Register	AT91_REG	 Reserved0[5]; 	// 	AT91_REG	 SMC2_MCR; 	// SMC2 Memory Control Register} AT91S_SMC2, *AT91PS_SMC2;// -------- SMC2_CSR : (SMC2 Offset: 0x0) Chip Select Register -------- #define AT91C_SMC2_DBW        ((unsigned int) 0x3 <<  0) // (SMC2) Data Bus Width#define 	AT91C_SMC2_DBW_                     ((unsigned int) 0x0) // (SMC2) Reserved#define 	AT91C_SMC2_DBW_16                   ((unsigned int) 0x1) // (SMC2) 16-bit.#define 	AT91C_SMC2_DBW_32                   ((unsigned int) 0x2) // (SMC2) 32-bit.#define AT91C_SMC2_NWS        ((unsigned int) 0x7 <<  2) // (SMC2) Number of Wait States#define 	AT91C_SMC2_NWS_0                    ((unsigned int) 0x0 <<  2) // (SMC2) NWS = 1#define 	AT91C_SMC2_NWS_1                    ((unsigned int) 0x1 <<  2) // (SMC2) NWS = 2#define 	AT91C_SMC2_NWS_2                    ((unsigned int) 0x2 <<  2) // (SMC2) NWS = 3#define 	AT91C_SMC2_NWS_3                    ((unsigned int) 0x3 <<  2) // (SMC2) NWS = 4#define 	AT91C_SMC2_NWS_4                    ((unsigned int) 0x4 <<  2) // (SMC2) NWS = 5#define 	AT91C_SMC2_NWS_5                    ((unsigned int) 0x5 <<  2) // (SMC2) NWS = 6#define 	AT91C_SMC2_NWS_6                    ((unsigned int) 0x6 <<  2) // (SMC2) NWS = 7#define 	AT91C_SMC2_NWS_7                    ((unsigned int) 0x7 <<  2) // (SMC2) NWS = 8#define AT91C_SMC2_WSE        ((unsigned int) 0x1 <<  5) // (SMC2) Wait State Enable#define AT91C_SMC2_MWS        ((unsigned int) 0x1 <<  6) // (SMC2) Multiply Wait States#define AT91C_SMC2_PAGES      ((unsigned int) 0x3 <<  7) // (SMC2) Page Size#define 	AT91C_SMC2_PAGES_1MB                  ((unsigned int) 0x0 <<  7) // (SMC2) 1MB BA20-BA31#define 	AT91C_SMC2_PAGES_4MB                  ((unsigned int) 0x1 <<  7) // (SMC2) 4MB BA22-BA31#define 	AT91C_SMC2_PAGES_16MB                 ((unsigned int) 0x2 <<  7) // (SMC2) 16MB BA24-BA31#define 	AT91C_SMC2_PAGES_                     ((unsigned int) 0x3 <<  7) // (SMC2) Reserved#define AT91C_SMC2_TDF        ((unsigned int) 0x7 <<  9) // (SMC2) Data Float Output Time#define 	AT91C_SMC2_TDF_0                    ((unsigned int) 0x0 <<  9) // (SMC2) Cycles After Transfer = 1#define 	AT91C_SMC2_TDF_1                    ((unsigned int) 0x1 <<  9) // (SMC2) Cycles After Transfer = 2#define 	AT91C_SMC2_TDF_2                    ((unsigned int) 0x2 <<  9) // (SMC2) Cycles After Transfer = 3#define 	AT91C_SMC2_TDF_3                    ((unsigned int) 0x3 <<  9) // (SMC2) Cycles After Transfer = 4#define 	AT91C_SMC2_TDF_4                    ((unsigned int) 0x4 <<  9) // (SMC2) Cycles After Transfer = 5#define 	AT91C_SMC2_TDF_5                    ((unsigned int) 0x5 <<  9) // (SMC2) Cycles After Transfer = 6#define 	AT91C_SMC2_TDF_6                    ((unsigned int) 0x6 <<  9) // (SMC2) Cycles After Transfer = 7#define 	AT91C_SMC2_TDF_7                    ((unsigned int) 0x7 <<  9) // (SMC2) Cycles After Transfer = 8#define AT91C_SMC2_BAT        ((unsigned int) 0x1 << 12) // (SMC2) Byte Access Type#define AT91C_SMC2_CSEN       ((unsigned int) 0x1 << 13) // (SMC2) Chip Select Enable#define AT91C_SMC2_BA         ((unsigned int) 0xFFF << 20) // (SMC2) Base Address// -------- SMC2_MCR : (SMC2 Offset: 0x24) Memory Control Register -------- #define AT91C_SMC2_DRP        ((unsigned int) 0x1 <<  4) // (SMC2) Data Read Protocol// *****************************************************************************//              SOFTWARE API DEFINITION  FOR SDRAM Controller Interface// *****************************************************************************typedef struct _AT91S_SDRC {	AT91_REG	 SDRC_MR; 	// SDRAM Controller Mode Register	AT91_REG	 SDRC_TR; 	// SDRAM Controller Refresh Timer Register	AT91_REG	 SDRC_CR; 	// SDRAM Controller Configuration Register	AT91_REG	 SDRC_16BITR; 	// SDRAM 16-bit Configuration Register	AT91_REG	 SDRC_ADDR; 	// SDRAM Base Address for SDCS} AT91S_SDRC, *AT91PS_SDRC;// -------- SDRC_MR : (SDRC Offset: 0x0) SDRAM Controller Mode Register -------- #define AT91C_SDRC_MODE       ((unsigned int) 0x7 <<  6) // (SDRC) Mode#define 	AT91C_SDRC_MODE_NORMAL_CMD           ((unsigned int) 0x0 <<  6) // (SDRC) Normal Mode#define 	AT91C_SDRC_MODE_NOP_CMD              ((unsigned int) 0x1 <<  6) // (SDRC) NOP Command#define 	AT91C_SDRC_MODE_PRCGALL_CMD          ((unsigned int) 0x2 <<  6) // (SDRC) All Banks Precharge Command#define 	AT91C_SDRC_MODE_LMR_CMD              ((unsigned int) 0x3 <<  6) // (SDRC) Load Mode Register Command#define 	AT91C_SDRC_MODE_RFSH_CMD             ((unsigned int) 0x4 <<  6) // (SDRC) Refresh Command// -------- SDRC_TR : (SDRC Offset: 0x4) SDRC Refresh Timer Register -------- #define AT91C_SDRC_COUNT      ((unsigned int) 0xFFF <<  0) // (SDRC) Refresh Counter// -------- SDRC_CR : (SDRC Offset: 0x8) SDRAM Configuration Register -------- #define AT91C_SDRC_NC         ((unsigned int) 0x3 <<  0) // (SDRC) Number of Column Bits#define 	AT91C_SDRC_NC_8                    ((unsigned int) 0x0) // (SDRC) 8 Bits#define 	AT91C_SDRC_NC_9                    ((unsigned int) 0x1) // (SDRC) 9 Bits#define 	AT91C_SDRC_NC_10                   ((unsigned int) 0x2) // (SDRC) 10 Bits#define 	AT91C_SDRC_NC_11                   ((unsigned int) 0x3) // (SDRC) 11 Bits#define AT91C_SDRC_NR         ((unsigned int) 0x3 <<  2) // (SDRC) Number of Row Bits#define 	AT91C_SDRC_NR_11                   ((unsigned int) 0x0 <<  2) // (SDRC) 11 Bits#define 	AT91C_SDRC_NR_12                   ((unsigned int) 0x1 <<  2) // (SDRC) 12 Bits#define 	AT91C_SDRC_NR_13                   ((unsigned int) 0x2 <<  2) // (SDRC) 13 Bits