#define AT91C_SDRC_NB         ((unsigned int) 0x1 <<  4) // (SDRC) Number of Banks#define 	AT91C_SDRC_NB_2_BANKS              ((unsigned int) 0x0 <<  4) // (SDRC) 2 banks#define 	AT91C_SDRC_NB_4_BANKS              ((unsigned int) 0x1 <<  4) // (SDRC) 4 banks#define AT91C_SDRC_TWR        ((unsigned int) 0xF <<  7) // (SDRC) Number of Write Recovery Time Cycles#define AT91C_SDRC_TRC        ((unsigned int) 0xF << 11) // (SDRC) Number of RAS Cycle Time Cycles#define AT91C_SDRC_TRP        ((unsigned int) 0xF << 15) // (SDRC) Number of RAS Precharge Time Cycles#define AT91C_SDRC_TRCD       ((unsigned int) 0xF << 19) // (SDRC) Number of RAS to CAS Delay Cycles#define AT91C_SDRC_TRAS       ((unsigned int) 0xF << 23) // (SDRC) Number of RAS Active Time Cycles// -------- SDRC_16BITR : (SDRC Offset: 0xc) SDRAM 16-bit Configuration Register -------- #define AT91C_SDRC_16BIT      ((unsigned int) 0x1 <<  0) // (SDRC) Mermory Width Configuration Bit// *****************************************************************************//              SOFTWARE API DEFINITION  FOR Peripheral Data Controller// *****************************************************************************typedef struct _AT91S_PDC {	AT91_REG	 PDC_RPR; 	// Receive Pointer Register	AT91_REG	 PDC_RCR; 	// Receive Counter Register	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register	AT91_REG	 PDC_TCR; 	// Transmit Counter Register} AT91S_PDC, *AT91PS_PDC;// *****************************************************************************//              SOFTWARE API DEFINITION  FOR Usart// *****************************************************************************typedef struct _AT91S_USART {	AT91_REG	 US_CR; 	// Control Register	AT91_REG	 US_MR; 	// Mode Register	AT91_REG	 US_IER; 	// Interrupt Enable Register	AT91_REG	 US_IDR; 	// Interrupt Disable Register	AT91_REG	 US_IMR; 	// Interrupt Mask Register	AT91_REG	 US_CSR; 	// Channel Status Register	AT91_REG	 US_RHR; 	// Receiver Holding Register	AT91_REG	 US_THR; 	// Transmitter Holding Register	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register	AT91_REG	 US_RTOR; 	// Receiver Time-out Register	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register	AT91_REG	 Reserved0[1]; 	// 	AT91_REG	 US_RPR; 	// Receive Pointer Register	AT91_REG	 US_RCR; 	// Receive Counter Register	AT91_REG	 US_TPR; 	// Transmit Pointer Register	AT91_REG	 US_TCR; 	// Transmit Counter Register	AT91_REG	 US_MC; 	// Modem Control Register	AT91_REG	 US_MS; 	// Modem Status Register} AT91S_USART, *AT91PS_USART;// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- #define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (USART) Reset Receiver#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (USART) Reset Transmitter#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (USART) Receiver Enable#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (USART) Receiver Disable#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (USART) Transmitter Enable#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (USART) Transmitter Disable#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (USART) Reset Status Bits// -------- US_MR : (USART Offset: 0x4) UART Mode Register -------- #define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock#define 	AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) // (USART) Clock#define 	AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) // (USART) fdiv1#define 	AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) // (USART) slow_clock (ARM)#define 	AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) // (USART) External (SCK)#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock#define 	AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) // (USART) Character Length: 5 bits#define 	AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) // (USART) Character Length: 6 bits#define 	AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) // (USART) Character Length: 7 bits#define 	AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) // (USART) Character Length: 8 bits#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (USART) Parity type#define 	AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (USART) Even Parity#define 	AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (USART) Odd Parity#define 	AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (USART) Parity forced to 0 (Space)#define 	AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (USART) Parity forced to 1 (Mark)#define 	AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (USART) No Parity#define 	AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (USART) Multi-drop mode#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits#define 	AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) // (USART) 1 stop bit#define 	AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits#define 	AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) // (USART) 2 stop bits#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (USART) Channel Mode#define 	AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (USART) Normal Mode: The USART channel operates as an RX/TX USART.#define 	AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (USART) Automatic Echo: Receiver Data Input is connected to the TXD pin.#define 	AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (USART) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.#define 	AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (USART) Remote Loopback: RXD pin is internally connected to TXD pin.// -------- US_IER : (USART Offset: 0x8) UART Interrupt Enable Register -------- #define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (USART) RXRDY Interrupt#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (USART) TXRDY Interrupt#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (USART) End of Receive Transfer Interrupt#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (USART) End of Transmit Interrupt#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (USART) Overrun Interrupt#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (USART) Framing Error Interrupt#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (USART) Parity Error Interrupt#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (USART) TXEMPTY Interrupt#define AT91C_US_DMSI         ((unsigned int) 0x1 << 10) // (USART) DMSI Interrupt// -------- US_IDR : (USART Offset: 0xc) UART Interrupt Disable Register -------- // -------- US_IMR : (USART Offset: 0x10) UART Interrupt Mask Register -------- // -------- US_CSR : (USART Offset: 0x14) UART Channel Status Register -------- // -------- US_MC : (USART Offset: 0x40) Modem Control Register -------- #define AT91C_US_DTR          ((unsigned int) 0x1 <<  0) // (USART) Data Terminal Ready#define AT91C_US_RTS          ((unsigned int) 0x1 <<  1) // (USART) Request To Send// -------- US_MS : (USART Offset: 0x44) Modem Status Register -------- #define AT91C_US_DCTS         ((unsigned int) 0x1 <<  0) // (USART) Delta clear to send#define AT91C_US_DDSR         ((unsigned int) 0x1 <<  1) // (USART) Delta Data Set Ready#define AT91C_US_TERI         ((unsigned int) 0x1 <<  2) // (USART) Trailing Edge Ring Indicator#define AT91C_US_DDCD         ((unsigned int) 0x1 <<  3) // (USART) Delta Data Carrier Detect#define AT91C_US_CTS          ((unsigned int) 0x1 <<  4) // (USART) Clear to Send#define AT91C_US_DSR          ((unsigned int) 0x1 <<  5) // (USART) Data Set Ready#define AT91C_US_RI           ((unsigned int) 0x1 <<  6) // (USART) Ring Indicator#define AT91C_US_DCD          ((unsigned int) 0x1 <<  7) // (USART) Data Carrier Detect// *****************************************************************************//              SOFTWARE API DEFINITION  FOR Serial Peripheral Interface// *****************************************************************************typedef struct _AT91S_SPI {	AT91_REG	 SPI_CR; 	// Control Register	AT91_REG	 SPI_MR; 	// Mode Register	AT91_REG	 SPI_RDR; 	// Receive Data Register	AT91_REG	 SPI_TDR; 	// Transmit Data Register	AT91_REG	 SPI_SR; 	// Status Register	AT91_REG	 SPI_IER; 	// Interrupt Enable Register	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register	AT91_REG	 SPI_RPR; 	// Receive Pointer Register	AT91_REG	 SPI_RCR; 	// Receive Counter Register	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register	AT91_REG	 SPI_TCR; 	// Transmit Counter Register	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register} AT91S_SPI, *AT91PS_SPI;// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- #define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) // (SPI) SPI Enable#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) // (SPI) SPI Disable#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) // (SPI) SPI Software reset// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- #define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) // (SPI) Master/Slave Mode#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) // (SPI) Peripheral Select#define 	AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) // (SPI) Fixed Peripheral Select#define 	AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) // (SPI) Variable Peripheral Select#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Decode#define AT91C_SPI_DIV32       ((unsigned int) 0x1 <<  3) // (SPI) Clock Selection#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) // (SPI) Mode Fault Detection#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) // (SPI) Clock Selection#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- #define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) // (SPI) Receive Data#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- #define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) // (SPI) Transmit Data#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- #define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) // (SPI) Receive Data Register Full#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) // (SPI) Transmit Data Register Empty#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) // (SPI) Mode Fault Error#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) // (SPI) Overrun Error Status#define AT91C_SPI_SPENDRX     ((unsigned int) 0x1 <<  4) // (SPI) End of Receiver Transfer#define AT91C_SPI_SPENDTX     ((unsigned int) 0x1 <<  5) // (SPI) End of Receiver Transfer#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) // (SPI) Enable Status// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- // -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- // -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- // -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- #define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) // (SPI) Clock Polarity#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) // (SPI) Clock Phase#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) // (SPI) Bits Per Transfer#define 	AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) // (SPI) 8 Bits Per transfer#define 	AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) // (SPI) 9 Bits Per transfer#define 	AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) // (SPI) 10 Bits Per transfer#define 	AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) // (SPI) 11 Bits Per transfer#define 	AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) // (SPI) 12 Bits Per transfer#define 	AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) // (SPI) 13 Bits Per transfer#define 	AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) // (SPI) 14 Bits Per transfer#define 	AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) // (SPI) 15 Bits Per transfer#define 	AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) // (SPI) 16 Bits Per transfer#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) // (SPI) Serial Clock Baud Rate#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) // (SPI) Serial Clock Baud Rate#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers// *****************************************************************************//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface// *****************************************************************************