AT91_REG	 EMAC_DRFC; 	// Discarded RX Frame Register	AT91_REG	 Reserved2[3]; 	// 	AT91_REG	 EMAC_HSH; 	// Hash Address High[63:32]	AT91_REG	 EMAC_HSL; 	// Hash Address Low[31:0]	AT91_REG	 EMAC_SA1L; 	// Specific Address 1 Low, First 4 bytes	AT91_REG	 EMAC_SA1H; 	// Specific Address 1 High, Last 2 bytes	AT91_REG	 EMAC_SA2L; 	// Specific Address 2 Low, First 4 bytes	AT91_REG	 EMAC_SA2H; 	// Specific Address 2 High, Last 2 bytes	AT91_REG	 EMAC_SA3L; 	// Specific Address 3 Low, First 4 bytes	AT91_REG	 EMAC_SA3H; 	// Specific Address 3 High, Last 2 bytes	AT91_REG	 EMAC_SA4L; 	// Specific Address 4 Low, First 4 bytes	AT91_REG	 EMAC_SA4H; 	// Specific Address 4 High, Last 2 bytesr} AT91S_EMAC, *AT91PS_EMAC;// -------- EMAC_CTL : (EMAC Offset: 0x0)  -------- #define AT91C_EMAC_LB         ((unsigned int) 0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.#define AT91C_EMAC_LBL        ((unsigned int) 0x1 <<  1) // (EMAC) Loopback local. #define AT91C_EMAC_RE         ((unsigned int) 0x1 <<  2) // (EMAC) Receive enable. #define AT91C_EMAC_TE         ((unsigned int) 0x1 <<  3) // (EMAC) Transmit enable. #define AT91C_EMAC_MPE        ((unsigned int) 0x1 <<  4) // (EMAC) Management port enable. #define AT91C_EMAC_CSR        ((unsigned int) 0x1 <<  5) // (EMAC) Clear statistics registers. #define AT91C_EMAC_ISR        ((unsigned int) 0x1 <<  6) // (EMAC) Increment statistics registers. #define AT91C_EMAC_WES        ((unsigned int) 0x1 <<  7) // (EMAC) Write enable for statistics registers. #define AT91C_EMAC_BP         ((unsigned int) 0x1 <<  8) // (EMAC) Back pressure. // -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- #define AT91C_EMAC_SPD        ((unsigned int) 0x1 <<  0) // (EMAC) Speed. #define AT91C_EMAC_FD         ((unsigned int) 0x1 <<  1) // (EMAC) Full duplex. #define AT91C_EMAC_BR         ((unsigned int) 0x1 <<  2) // (EMAC) Bit rate. #define AT91C_EMAC_CAF        ((unsigned int) 0x1 <<  4) // (EMAC) Copy all frames. #define AT91C_EMAC_NBC        ((unsigned int) 0x1 <<  5) // (EMAC) No broadcast. #define AT91C_EMAC_MTI        ((unsigned int) 0x1 <<  6) // (EMAC) Multicast hash enable#define AT91C_EMAC_UNI        ((unsigned int) 0x1 <<  7) // (EMAC) Unicast hash enable. #define AT91C_EMAC_BIG        ((unsigned int) 0x1 <<  8) // (EMAC) Receive 1522 bytes. #define AT91C_EMAC_EAE        ((unsigned int) 0x1 <<  9) // (EMAC) External address match enable. #define AT91C_EMAC_CLK        ((unsigned int) 0x3 << 10) // (EMAC) #define 	AT91C_EMAC_CLK_HCLK_8               ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8#define 	AT91C_EMAC_CLK_HCLK_16              ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16#define 	AT91C_EMAC_CLK_HCLK_32              ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32#define 	AT91C_EMAC_CLK_HCLK_64              ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64#define AT91C_EMAC_RTY        ((unsigned int) 0x1 << 12) // (EMAC) // -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- #define AT91C_EMAC_LINK       ((unsigned int) 0x1 <<  0) // (EMAC) #define AT91C_EMAC_MDIO       ((unsigned int) 0x1 <<  1) // (EMAC) #define AT91C_EMAC_IDLE       ((unsigned int) 0x1 <<  2) // (EMAC) // -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- #define AT91C_EMAC_LEN        ((unsigned int) 0x7FF <<  0) // (EMAC) #define AT91C_EMAC_NCRC       ((unsigned int) 0x1 << 15) // (EMAC) // -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- #define AT91C_EMAC_OVR        ((unsigned int) 0x1 <<  0) // (EMAC) #define AT91C_EMAC_COL        ((unsigned int) 0x1 <<  1) // (EMAC) #define AT91C_EMAC_RLE        ((unsigned int) 0x1 <<  2) // (EMAC) #define AT91C_EMAC_TXIDLE     ((unsigned int) 0x1 <<  3) // (EMAC) #define AT91C_EMAC_BNQ        ((unsigned int) 0x1 <<  4) // (EMAC) #define AT91C_EMAC_COMP       ((unsigned int) 0x1 <<  5) // (EMAC) #define AT91C_EMAC_UND        ((unsigned int) 0x1 <<  6) // (EMAC) // -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- #define AT91C_EMAC_BNA        ((unsigned int) 0x1 <<  0) // (EMAC) #define AT91C_EMAC_REC        ((unsigned int) 0x1 <<  1) // (EMAC) #define AT91C_EMAC_RSR_OVR    ((unsigned int) 0x1 <<  2) // (EMAC) // -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- #define AT91C_EMAC_DONE       ((unsigned int) 0x1 <<  0) // (EMAC) #define AT91C_EMAC_RCOM       ((unsigned int) 0x1 <<  1) // (EMAC) #define AT91C_EMAC_RBNA       ((unsigned int) 0x1 <<  2) // (EMAC) #define AT91C_EMAC_TOVR       ((unsigned int) 0x1 <<  3) // (EMAC) #define AT91C_EMAC_TUND       ((unsigned int) 0x1 <<  4) // (EMAC) #define AT91C_EMAC_RTRY       ((unsigned int) 0x1 <<  5) // (EMAC) #define AT91C_EMAC_TBRE       ((unsigned int) 0x1 <<  6) // (EMAC) #define AT91C_EMAC_TCOM       ((unsigned int) 0x1 <<  7) // (EMAC) #define AT91C_EMAC_TIDLE      ((unsigned int) 0x1 <<  8) // (EMAC) #define AT91C_EMAC_ROVR       ((unsigned int) 0x1 << 10) // (EMAC) #define AT91C_EMAC_ABT        ((unsigned int) 0x1 << 11) // (EMAC) // -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- // -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- // -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- // -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- #define AT91C_EMAC_DATA       ((unsigned int) 0xFFFF <<  0) // (EMAC) #define AT91C_EMAC_CODE       ((unsigned int) 0x3 << 16) // (EMAC) #define 	AT91C_EMAC_CODE_802_3                ((unsigned int) 0x2 << 16) // (EMAC) IEEE standard 802.3#define AT91C_EMAC_REGA       ((unsigned int) 0x1F << 18) // (EMAC) #define AT91C_EMAC_PHYA       ((unsigned int) 0x1F << 23) // (EMAC) #define AT91C_EMAC_RW         ((unsigned int) 0x3 << 28) // (EMAC) #define 	AT91C_EMAC_RW_W                    ((unsigned int) 0x1 << 28) // (EMAC) Write to Phy#define 	AT91C_EMAC_RW_R                    ((unsigned int) 0x2 << 28) // (EMAC) Read from Phy#define AT91C_EMAC_HIGH       ((unsigned int) 0x1 << 30) // (EMAC) #define AT91C_EMAC_LOW        ((unsigned int) 0x1 << 31) // (EMAC) // *****************************************************************************//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler// *****************************************************************************typedef struct _AT91S_PIO {	AT91_REG	 PIO_PER; 	// PIO Enable Register	AT91_REG	 PIO_PDR; 	// PIO Disable Register	AT91_REG	 PIO_PSR; 	// PIO Status Register	AT91_REG	 Reserved0[1]; 	// 	AT91_REG	 PIO_OER; 	// Output Enable Register	AT91_REG	 PIO_ODR; 	// Output Disable Registerr	AT91_REG	 PIO_OSR; 	// Output Status Register	AT91_REG	 Reserved1[5]; 	// 	AT91_REG	 PIO_SODR; 	// Set Output Data Register	AT91_REG	 PIO_CODR; 	// Clear Output Data Register	AT91_REG	 PIO_ODSR; 	// Output Data Status Register	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register	AT91_REG	 PIO_IER; 	// Interrupt Enable Register	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register	AT91_REG	 PIO_ISR; 	// Interrupt Status Register} AT91S_PIO, *AT91PS_PIO;// *****************************************************************************//              SOFTWARE API DEFINITION  FOR System Controller Interface// *****************************************************************************typedef struct _AT91S_SYSC {	AT91_REG	 SYSC_MD; 	// Mode Register	AT91_REG	 SYSC_ID; 	// ID Register	AT91_REG	 Reserved0[1]; 	// 	AT91_REG	 SYSC_CLKF; 	// Clock Status Register} AT91S_SYSC, *AT91PS_SYSC;// -------- SYSC_MD : (SYSC Offset: 0x0) Mode Register -------- #define AT91C_SYSC_RM         ((unsigned int) 0x1 <<  0) // (SYSC) Remap#define AT91C_SYSC_DSPRST     ((unsigned int) 0x1 <<  1) // (SYSC) DSP Subsystem Reset#define AT91C_SYSC_IDSPCLK    ((unsigned int) 0x1 <<  3) // (SYSC) Inhibit DSP Subsystem Clock#define AT91C_SYSC_LP         ((unsigned int) 0x1 <<  6) // (SYSC) Low Power Mode#define AT91C_SYSC_SA         ((unsigned int) 0x1 <<  7) // (SYSC) Slow ARM Mode#define AT91C_SYSC_LPCS       ((unsigned int) 0x7 <<  8) // (SYSC) Low Power Clock Select#define 	AT91C_SYSC_LPCS_0                    ((unsigned int) 0x0 <<  8) // (SYSC) Divisor = 2 ACLK = 8MHz#define 	AT91C_SYSC_LPCS_1                    ((unsigned int) 0x1 <<  8) // (SYSC) Divisor = 16 ACLK = 1MHz#define 	AT91C_SYSC_LPCS_2                    ((unsigned int) 0x2 <<  8) // (SYSC) Divisor = 64 ACLK = 250KHz#define 	AT91C_SYSC_LPCS_3                    ((unsigned int) 0x3 <<  8) // (SYSC) Divisor = 512 ACLK = 31.25KHz#define AT91C_SYSC_CRST       ((unsigned int) 0x1 << 14) // (SYSC) Codec Interface Reset// -------- SYSC_ID : (SYSC Offset: 0x4) ID Register -------- #define AT91C_SYSC_IDENT      ((unsigned int) 0xFFFF <<  0) // (SYSC) Identifier#define AT91C_SYSC_PKG        ((unsigned int) 0x1 <<  1) // (SYSC) Package// *****************************************************************************//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller// *****************************************************************************typedef struct _AT91S_AIC {	AT91_REG	 AIC_SMR[32]; 	// Source Mode egister	AT91_REG	 AIC_SVR[32]; 	// Source Vector egister	AT91_REG	 AIC_IVR; 	// IRQ Vector Register	AT91_REG	 AIC_FVR; 	// FIQ Vector Register	AT91_REG	 AIC_ISR; 	// Interrupt Status Register	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register	AT91_REG	 Reserved0[2]; 	// 	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command egister	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register	AT91_REG	 AIC_SPU; 	// Spurious Vector Register} AT91S_AIC, *AT91PS_AIC;// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- #define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level#define 	AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level#define 	AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type#define 	AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label Level Sensitive#define 	AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Edge triggered#define 	AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       ((unsigned int) 0x2 <<  5) // (AIC) External Sources Code Label High-level Sensitive#define 	AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    ((unsigned int) 0x3 <<  5) // (AIC) External Sources Code Label Positive Edge triggered// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- #define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status// *****************************************************************************//               REGISTER ADDRESS DEFINITION FOR AT91C221// *****************************************************************************// ========== Register definition for SYS peripheral ========== // ========== Register definition for SMC2 peripheral ========== #define AT91C_SMC2_CSR  ((AT91_REG *) 	0xFF004000) // (SMC2) SMC2 Chip Select Register#define AT91C_SMC2_MCR  ((AT91_REG *) 	0xFF004024) // (SMC2) SMC2 Memory Control Register// ========== Register definition for SDRC peripheral ========== #define AT91C_SDRC_16BITR ((AT91_REG *) 	0xFF00800C) // (SDRC) SDRAM 16-bit Configuration Register