#define RDAR1	   __REG(0x40900018)  /* Wristwatch Day Alarm Reg 1 */#define RDAR2	   __REG(0x40900020)  /* Wristwatch Day Alarm Reg 2 */#define RYAR1	   __REG(0x4090001C)  /* Wristwatch Year Alarm Reg 1 */#define RYAR2	   __REG(0x40900024)  /* Wristwatch Year Alarm Reg 2 */#define SWAR1	   __REG(0x4090002C)  /* Stopwatch Alarm Register 1 */#define SWAR2	   __REG(0x40900030)  /* Stopwatch Alarm Register 2 */#define PIAR	   __REG(0x40900038)  /* Periodic Interrupt Alarm Register */#define RDCR	   __REG(0x40900010)  /* RTC Day Count Register. */#define RYCR	   __REG(0x40900014)  /* RTC Year Count Register. */#define SWCR	   __REG(0x40900028)  /* Stopwatch Count Register */#define RTCPICR	   __REG(0x40900034)  /* Periodic Interrupt Counter Register */#define RTSR_PICE  (1 << 15)   /* Peridoc interrupt count enable */#define RTSR_PIALE (1 << 14)   /* Peridoc interrupt Alarm enable */#define RTSR_PIAL  (1 << 13)   /* Peridoc  interrupt Alarm status */#define RTSR_HZE	(1 << 3)	/* HZ interrupt enable */#define RTSR_ALE	(1 << 2)	/* RTC alarm interrupt enable */#define RTSR_HZ		(1 << 1)	/* HZ rising-edge detected */#define RTSR_AL		(1 << 0)	/* RTC alarm detected *//* * OS Timer & Match Registers */#define OSMR0		__REG(0x40A00000)  /* */#define OSMR1		__REG(0x40A00004)  /* */#define OSMR2		__REG(0x40A00008)  /* */#define OSMR3		__REG(0x40A0000C)  /* */#define OSCR		__REG(0x40A00010)  /* OS Timer Counter Register */#define OSSR		__REG(0x40A00014)  /* OS Timer Status Register */#define OWER		__REG(0x40A00018)  /* OS Timer Watchdog Enable Register */#define OIER		__REG(0x40A0001C)  /* OS Timer Interrupt Enable Register */#define OSSR_M3		(1 << 3)	/* Match status channel 3 */#define OSSR_M2		(1 << 2)	/* Match status channel 2 */#define OSSR_M1		(1 << 1)	/* Match status channel 1 */#define OSSR_M0		(1 << 0)	/* Match status channel 0 */#define OWER_WME	(1 << 0)	/* Watchdog Match Enable */#define OIER_E3		(1 << 3)	/* Interrupt enable channel 3 */#define OIER_E2		(1 << 2)	/* Interrupt enable channel 2 */#define OIER_E1		(1 << 1)	/* Interrupt enable channel 1 */#define OIER_E0		(1 << 0)	/* Interrupt enable channel 0 *//* * Pulse Width Modulator */#define PWM_CTRL0	__REG(0x40B00000)  /* PWM 0 Control Register */#define PWM_PWDUTY0	__REG(0x40B00004)  /* PWM 0 Duty Cycle Register */#define PWM_PERVAL0	__REG(0x40B00008)  /* PWM 0 Period Control Register */#define PWM_CTRL1	__REG(0x40C00000)  /* PWM 1Control Register */#define PWM_PWDUTY1	__REG(0x40C00004)  /* PWM 1 Duty Cycle Register */#define PWM_PERVAL1	__REG(0x40C00008)  /* PWM 1 Period Control Register *//* * Interrupt Controller */#define ICIP		__REG(0x40D00000)  /* Interrupt Controller IRQ Pending Register */#define ICMR		__REG(0x40D00004)  /* Interrupt Controller Mask Register */#define ICLR		__REG(0x40D00008)  /* Interrupt Controller Level Register */#define ICFP		__REG(0x40D0000C)  /* Interrupt Controller FIQ Pending Register */#define ICPR		__REG(0x40D00010)  /* Interrupt Controller Pending Register */#define ICCR		__REG(0x40D00014)  /* Interrupt Controller Control Register *//* * General Purpose I/O */#define GPLR0		__REG(0x40E00000)  /* GPIO Pin-Level Register GPIO<31:0> */#define GPLR1		__REG(0x40E00004)  /* GPIO Pin-Level Register GPIO<63:32> */#define GPLR2		__REG(0x40E00008)  /* GPIO Pin-Level Register GPIO<80:64> */#define GPDR0		__REG(0x40E0000C)  /* GPIO Pin Direction Register GPIO<31:0> */#define GPDR1		__REG(0x40E00010)  /* GPIO Pin Direction Register GPIO<63:32> */#define GPDR2		__REG(0x40E00014)  /* GPIO Pin Direction Register GPIO<80:64> */#define GPSR0		__REG(0x40E00018)  /* GPIO Pin Output Set Register GPIO<31:0> */#define GPSR1		__REG(0x40E0001C)  /* GPIO Pin Output Set Register GPIO<63:32> */#define GPSR2		__REG(0x40E00020)  /* GPIO Pin Output Set Register GPIO<80:64> */#define GPCR0		__REG(0x40E00024)  /* GPIO Pin Output Clear Register GPIO<31:0> */#define GPCR1		__REG(0x40E00028)  /* GPIO Pin Output Clear Register GPIO <63:32> */#define GPCR2		__REG(0x40E0002C)  /* GPIO Pin Output Clear Register GPIO <80:64> */#define GRER0		__REG(0x40E00030)  /* GPIO Rising-Edge Detect Register GPIO<31:0> */#define GRER1		__REG(0x40E00034)  /* GPIO Rising-Edge Detect Register GPIO<63:32> */#define GRER2		__REG(0x40E00038)  /* GPIO Rising-Edge Detect Register GPIO<80:64> */#define GFER0		__REG(0x40E0003C)  /* GPIO Falling-Edge Detect Register GPIO<31:0> */#define GFER1		__REG(0x40E00040)  /* GPIO Falling-Edge Detect Register GPIO<63:32> */#define GFER2		__REG(0x40E00044)  /* GPIO Falling-Edge Detect Register GPIO<80:64> */#define GEDR0		__REG(0x40E00048)  /* GPIO Edge Detect Status Register GPIO<31:0> */#define GEDR1		__REG(0x40E0004C)  /* GPIO Edge Detect Status Register GPIO<63:32> */#define GEDR2		__REG(0x40E00050)  /* GPIO Edge Detect Status Register GPIO<80:64> */#define GAFR0_L		__REG(0x40E00054)  /* GPIO Alternate Function Select Register GPIO<15:0> */#define GAFR0_U		__REG(0x40E00058)  /* GPIO Alternate Function Select Register GPIO<31:16> */#define GAFR1_L		__REG(0x40E0005C)  /* GPIO Alternate Function Select Register GPIO<47:32> */#define GAFR1_U		__REG(0x40E00060)  /* GPIO Alternate Function Select Register GPIO<63:48> */#define GAFR2_L		__REG(0x40E00064)  /* GPIO Alternate Function Select Register GPIO<79:64> */#define GAFR2_U		__REG(0x40E00068)  /* GPIO Alternate Function Select Register GPIO 80 *//* More handy macros.  The argument is a literal GPIO number. */#define GPIO_bit(x)	(1 << ((x) & 0x1f))#ifdef CONFIG_PXA27X/* Interrupt Controller */#define ICIP2		__REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */#define ICMR2		__REG(0x40D000A0)  /* Interrupt Controller Mask Register 2 */#define ICLR2		__REG(0x40D000A4)  /* Interrupt Controller Level Register 2 */#define ICFP2		__REG(0x40D000A8)  /* Interrupt Controller FIQ Pending Register 2 */#define ICPR2		__REG(0x40D000AC)  /* Interrupt Controller Pending Register 2 */#define _GPLR(x)	__REG2(0x40E00000, ((x) & 0x60) >> 3)#define _GPDR(x)	__REG2(0x40E0000C, ((x) & 0x60) >> 3)#define _GPSR(x)	__REG2(0x40E00018, ((x) & 0x60) >> 3)#define _GPCR(x)	__REG2(0x40E00024, ((x) & 0x60) >> 3)#define _GRER(x)	__REG2(0x40E00030, ((x) & 0x60) >> 3)#define _GFER(x)	__REG2(0x40E0003C, ((x) & 0x60) >> 3)#define _GEDR(x)	__REG2(0x40E00048, ((x) & 0x60) >> 3)#define _GAFR(x)	__REG2(0x40E00054, ((x) & 0x70) >> 2)#define GPLR(x)		((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3)#define GPDR(x)		((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3)#define GPSR(x)		((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3)#define GPCR(x)		((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3)#define GRER(x)		((((x) & 0x7f) < 96) ? _GRER(x) : GRER3)#define GFER(x)		((((x) & 0x7f) < 96) ? _GFER(x) : GFER3)#define GEDR(x)		((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3)#define GAFR(x)		((((x) & 0x7f) < 96) ? _GAFR(x) : \			 ((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U))#else#define GPLR(x)		__REG2(0x40E00000, ((x) & 0x60) >> 3)#define GPDR(x)		__REG2(0x40E0000C, ((x) & 0x60) >> 3)#define GPSR(x)		__REG2(0x40E00018, ((x) & 0x60) >> 3)#define GPCR(x)		__REG2(0x40E00024, ((x) & 0x60) >> 3)#define GRER(x)		__REG2(0x40E00030, ((x) & 0x60) >> 3)#define GFER(x)		__REG2(0x40E0003C, ((x) & 0x60) >> 3)#define GEDR(x)		__REG2(0x40E00048, ((x) & 0x60) >> 3)#define GAFR(x)		__REG2(0x40E00054, ((x) & 0x70) >> 2)#endif/* GPIO alternate function assignments */#define GPIO1_RST		1	/* reset */#define GPIO6_MMCCLK		6	/* MMC Clock */#define GPIO8_48MHz		7	/* 48 MHz clock output */#define GPIO8_MMCCS0		8	/* MMC Chip Select 0 */#define GPIO9_MMCCS1		9	/* MMC Chip Select 1 */#define GPIO10_RTCCLK		10	/* real time clock (1 Hz) */#define GPIO11_3_6MHz		11	/* 3.6 MHz oscillator out */#define GPIO12_32KHz		12	/* 32 kHz out */#define GPIO13_MBGNT		13	/* memory controller grant */#define GPIO14_MBREQ		14	/* alternate bus master request */#define GPIO15_nCS_1		15	/* chip select 1 */#define GPIO16_PWM0		16	/* PWM0 output */#define GPIO17_PWM1		17	/* PWM1 output */#define GPIO18_RDY		18	/* Ext. Bus Ready */#define GPIO19_DREQ1		19	/* External DMA Request */#define GPIO20_DREQ0		20	/* External DMA Request */#define GPIO23_SCLK		23	/* SSP clock */#define GPIO24_SFRM		24	/* SSP Frame */#define GPIO25_STXD		25	/* SSP transmit */#define GPIO26_SRXD		26	/* SSP receive */#define GPIO27_SEXTCLK		27	/* SSP ext_clk */#define GPIO28_BITCLK		28	/* AC97/I2S bit_clk */#define GPIO29_SDATA_IN		29	/* AC97 Sdata_in0 / I2S Sdata_in */#define GPIO30_SDATA_OUT	30	/* AC97/I2S Sdata_out */#define GPIO31_SYNC		31	/* AC97/I2S sync */#define GPIO32_SDATA_IN1	32	/* AC97 Sdata_in1 */#define GPIO33_nCS_5		33	/* chip select 5 */#define GPIO34_FFRXD		34	/* FFUART receive */#define GPIO34_MMCCS0		34	/* MMC Chip Select 0 */#define GPIO35_FFCTS		35	/* FFUART Clear to send */#define GPIO36_FFDCD		36	/* FFUART Data carrier detect */#define GPIO37_FFDSR		37	/* FFUART data set ready */#define GPIO38_FFRI		38	/* FFUART Ring Indicator */#define GPIO39_MMCCS1		39	/* MMC Chip Select 1 */#define GPIO39_FFTXD		39	/* FFUART transmit data */#define GPIO40_FFDTR		40	/* FFUART data terminal Ready */#define GPIO41_FFRTS		41	/* FFUART request to send */#define GPIO42_BTRXD		42	/* BTUART receive data */#define GPIO43_BTTXD		43	/* BTUART transmit data */#define GPIO44_BTCTS		44	/* BTUART clear to send */#define GPIO45_BTRTS		45	/* BTUART request to send */#define GPIO46_ICPRXD		46	/* ICP receive data */#define GPIO46_STRXD		46	/* STD_UART receive data */#define GPIO47_ICPTXD		47	/* ICP transmit data */#define GPIO47_STTXD		47	/* STD_UART transmit data */#define GPIO48_nPOE		48	/* Output Enable for Card Space */#define GPIO49_nPWE		49	/* Write Enable for Card Space */#define GPIO50_nPIOR		50	/* I/O Read for Card Space */#define GPIO51_nPIOW		51	/* I/O Write for Card Space */#define GPIO52_nPCE_1		52	/* Card Enable for Card Space */#define GPIO53_nPCE_2		53	/* Card Enable for Card Space */#define GPIO53_MMCCLK		53	/* MMC Clock */#define GPIO54_MMCCLK		54	/* MMC Clock */#define GPIO54_pSKTSEL		54	/* Socket Select for Card Space */#define GPIO55_nPREG		55	/* Card Address bit 26 */#define GPIO56_nPWAIT		56	/* Wait signal for Card Space */#define GPIO57_nIOIS16		57	/* Bus Width select for I/O Card Space */#define GPIO58_LDD_0		58	/* LCD data pin 0 */#define GPIO59_LDD_1		59	/* LCD data pin 1 */#define GPIO60_LDD_2		60	/* LCD data pin 2 */#define GPIO61_LDD_3		61	/* LCD data pin 3 */#define GPIO62_LDD_4		62	/* LCD data pin 4 */#define GPIO63_LDD_5		63	/* LCD data pin 5 */#define GPIO64_LDD_6		64	/* LCD data pin 6 */#define GPIO65_LDD_7		65	/* LCD data pin 7 */#define GPIO66_LDD_8		66	/* LCD data pin 8 */#define GPIO66_MBREQ		66	/* alternate bus master req */#define GPIO67_LDD_9		67	/* LCD data pin 9 */#define GPIO67_MMCCS0		67	/* MMC Chip Select 0 */#define GPIO68_LDD_10		68	/* LCD data pin 10 */#define GPIO68_MMCCS1		68	/* MMC Chip Select 1 */#define GPIO69_LDD_11		69	/* LCD data pin 11 */#define GPIO69_MMCCLK		69	/* MMC_CLK */#define GPIO70_LDD_12		70	/* LCD data pin 12 */#define GPIO70_RTCCLK		70	/* Real Time clock (1 Hz) */#define GPIO71_LDD_13		71	/* LCD data pin 13 */#define GPIO71_3_6MHz		71	/* 3.6 MHz Oscillator clock */#define GPIO72_LDD_14		72	/* LCD data pin 14 */#define GPIO72_32kHz		72	/* 32 kHz clock */#define GPIO73_LDD_15		73	/* LCD data pin 15 */#define GPIO73_MBGNT		73	/* Memory controller grant */#define GPIO74_LCD_FCLK		74	/* LCD Frame clock */#define GPIO75_LCD_LCLK		75	/* LCD line clock */#define GPIO76_LCD_PCLK		76	/* LCD Pixel clock */#define GPIO77_LCD_ACBIAS	77	/* LCD AC Bias */#define GPIO78_nCS_2		78	/* chip select 2 */#define GPIO79_nCS_3		79	/* chip select 3 */#define GPIO80_nCS_4		80	/* chip select 4 *//* GPIO alternate function mode & direction */#define GPIO_IN			0x000#define GPIO_OUT		0x080#define GPIO_ALT_FN_1_IN	0x100#define GPIO_ALT_FN_1_OUT	0x180#define GPIO_ALT_FN_2_IN	0x200#define GPIO_ALT_FN_2_OUT	0x280#define GPIO_ALT_FN_3_IN	0x300#define GPIO_ALT_FN_3_OUT	0x380#define GPIO_MD_MASK_NR		0x07f#define GPIO_MD_MASK_DIR	0x080#define GPIO_MD_MASK_FN		0x300#define GPIO1_RTS_MD		( 1 | GPIO_ALT_FN_1_IN)#define GPIO6_MMCCLK_MD		( 6 | GPIO_ALT_FN_1_OUT)#define GPIO8_48MHz_MD		( 8 | GPIO_ALT_FN_1_OUT)#define GPIO8_MMCCS0_MD		( 8 | GPIO_ALT_FN_1_OUT)#define GPIO9_MMCCS1_MD		( 9 | GPIO_ALT_FN_1_OUT)#define GPIO10_RTCCLK_MD	(10 | GPIO_ALT_FN_1_OUT)#define GPIO11_3_6MHz_MD	(11 | GPIO_ALT_FN_1_OUT)#define GPIO12_32KHz_MD		(12 | GPIO_ALT_FN_1_OUT)#define GPIO13_MBGNT_MD		(13 | GPIO_ALT_FN_2_OUT)#define GPIO14_MBREQ_MD		(14 | GPIO_ALT_FN_1_IN)#define GPIO15_nCS_1_MD		(15 | GPIO_ALT_FN_2_OUT)