?? sdram_init.c
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/*------------------------------------------------------------------------------------------------------------------------------*/ for (i = 2; i <= 35; i++) { switch (i) { case 2: /* Memory type (DDR / SDRAM) */ dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM;#ifdef DEBUG if (dimmInfo->memoryType == 0) DP (printf ("Dram_type in slot %d is: SDRAM\n", dimmInfo->slot)); if (dimmInfo->memoryType == 1) DP (printf ("Dram_type in slot %d is: DDRAM\n", dimmInfo->slot));#endif break;/*------------------------------------------------------------------------------------------------------------------------------*/ case 3: /* Number Of Row Addresses */ dimmInfo->numOfRowAddresses = data[i]; DP (printf ("Module Number of row addresses: %d\n", dimmInfo->numOfRowAddresses)); break;/*------------------------------------------------------------------------------------------------------------------------------*/ case 4: /* Number Of Column Addresses */ dimmInfo->numOfColAddresses = data[i]; DP (printf ("Module Number of col addresses: %d\n", dimmInfo->numOfColAddresses)); break;/*------------------------------------------------------------------------------------------------------------------------------*/ case 5: /* Number Of Module Banks */ dimmInfo->numOfModuleBanks = data[i]; DP (printf ("Number of Banks on Mod. : %d\n", dimmInfo->numOfModuleBanks)); break;/*------------------------------------------------------------------------------------------------------------------------------*/ case 6: /* Data Width */ dimmInfo->dataWidth = data[i]; DP (printf ("Module Data Width: %d\n", dimmInfo->dataWidth)); break;/*------------------------------------------------------------------------------------------------------------------------------*/ case 8: /* Voltage Interface */ switch (data[i]) { case 0x0: dimmInfo->voltageInterface = TTL_5V_TOLERANT; DP (printf ("Module is TTL_5V_TOLERANT\n")); break; case 0x1: dimmInfo->voltageInterface = LVTTL; DP (printf ("Module is LVTTL\n")); break; case 0x2: dimmInfo->voltageInterface = HSTL_1_5V; DP (printf ("Module is TTL_5V_TOLERANT\n")); break; case 0x3: dimmInfo->voltageInterface = SSTL_3_3V; DP (printf ("Module is HSTL_1_5V\n")); break; case 0x4: dimmInfo->voltageInterface = SSTL_2_5V; DP (printf ("Module is SSTL_2_5V\n")); break; default: dimmInfo->voltageInterface = VOLTAGE_UNKNOWN; DP (printf ("Module is VOLTAGE_UNKNOWN\n")); break; } break;/*------------------------------------------------------------------------------------------------------------------------------*/ case 9: /* Minimum Cycle Time At Max CasLatancy */ shift = (dimmInfo->memoryType == DDR) ? 4 : 2; mult = (dimmInfo->memoryType == DDR) ? 10 : 25; maskLeftOfPoint = (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; maskRightOfPoint = (dimmInfo->memoryType == DDR) ? 0xf : 0x03; leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; rightOfPoint = (data[i] & maskRightOfPoint) * mult; dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP = leftOfPoint; dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP = rightOfPoint; DP (printf ("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n", leftOfPoint, rightOfPoint)); break;/*------------------------------------------------------------------------------------------------------------------------------*/ case 10: /* Clock To Data Out */ div = (dimmInfo->memoryType == DDR) ? 100 : 10; time_tmp = (((data[i] & 0xf0) >> 4) * 10) + ((data[i] & 0x0f)); leftOfPoint = time_tmp / div; rightOfPoint = time_tmp % div; dimmInfo->clockToDataOut_LoP = leftOfPoint; dimmInfo->clockToDataOut_RoP = rightOfPoint; DP (printf ("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->clockToDataOut */ break;/*------------------------------------------------------------------------------------------------------------------------------*/#ifdef CONFIG_ECC case 11: /* Error Check Type */ dimmInfo->errorCheckType = data[i]; DP (printf ("Error Check Type (0=NONE): %d\n", dimmInfo->errorCheckType)); break;#endif/*------------------------------------------------------------------------------------------------------------------------------*/ case 12: /* Refresh Interval */ dimmInfo->RefreshInterval = data[i]; DP (printf ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n", dimmInfo->RefreshInterval)); break;/*------------------------------------------------------------------------------------------------------------------------------*/ case 13: /* Sdram Width */ dimmInfo->sdramWidth = data[i]; DP (printf ("Sdram Width: %d\n", dimmInfo->sdramWidth)); break;/*------------------------------------------------------------------------------------------------------------------------------*/ case 14: /* Error Check Data Width */ dimmInfo->errorCheckDataWidth = data[i]; DP (printf ("Error Check Data Width: %d\n", dimmInfo->errorCheckDataWidth)); break;/*------------------------------------------------------------------------------------------------------------------------------*/ case 15: /* Minimum Clock Delay */ dimmInfo->minClkDelay = data[i]; DP (printf ("Minimum Clock Delay: %d\n", dimmInfo->minClkDelay)); break;/*------------------------------------------------------------------------------------------------------------------------------*/ case 16: /* Burst Length Supported */ /******-******-******-******* * bit3 | bit2 | bit1 | bit0 * *******-******-******-******* burst length = * 8 | 4 | 2 | 1 * ***************************** If for example bit0 and bit2 are set, the burst length supported are 1 and 4. */ dimmInfo->burstLengthSupported = data[i];#ifdef DEBUG DP (printf ("Burst Length Supported: ")); if (dimmInfo->burstLengthSupported & 0x01) DP (printf ("1, ")); if (dimmInfo->burstLengthSupported & 0x02) DP (printf ("2, ")); if (dimmInfo->burstLengthSupported & 0x04) DP (printf ("4, ")); if (dimmInfo->burstLengthSupported & 0x08) DP (printf ("8, ")); DP (printf (" Bit \n"));#endif break;/*------------------------------------------------------------------------------------------------------------------------------*/ case 17: /* Number Of Banks On Each Device */ dimmInfo->numOfBanksOnEachDevice = data[i]; DP (printf ("Number Of Banks On Each Chip: %d\n", dimmInfo->numOfBanksOnEachDevice)); break;/*------------------------------------------------------------------------------------------------------------------------------*/ case 18: /* Suported Cas Latencies */ /* DDR: *******-******-******-******-******-******-******-******* * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * *******-******-******-******-******-******-******-******* CAS = * TBD | TBD | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * ********************************************************* SDRAM: *******-******-******-******-******-******-******-******* * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * *******-******-******-******-******-******-******-******* CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * ********************************************************/ dimmInfo->suportedCasLatencies = data[i];#ifdef DEBUG DP (printf ("Suported Cas Latencies: (CL) ")); if (dimmInfo->memoryType == 0) { /* SDRAM */ for (k = 0; k <= 7; k++) { if (dimmInfo-> suportedCasLatencies & (1 << k)) DP (printf ("%d, ", k + 1)); } } else { /* DDR-RAM */ if (dimmInfo->suportedCasLatencies & 1) DP (printf ("1, ")); if (dimmInfo->suportedCasLatencies & 2) DP (printf ("1.5, ")); if (dimmInfo->suportedCasLatencies & 4) DP (printf ("2, ")); if (dimmInfo->suportedCasLatencies & 8) DP (printf ("2.5, ")); if (dimmInfo->suportedCasLatencies & 16) DP (printf ("3, ")); if (dimmInfo->suportedCasLatencies & 32) DP (printf ("3.5, ")); } DP (printf ("\n"));#endif /* Calculating MAX CAS latency */ for (j = 7; j > 0; j--) { if (((dimmInfo-> suportedCasLatencies >> j) & 0x1) == 1) { switch (dimmInfo->memoryType) { case DDR: /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */ switch (j) { case 7: DP (printf ("Max. Cas Latencies (DDR): ERROR !!!\n")); dimmInfo-> maxClSupported_DDR = DDR_CL_FAULT; hang (); break; case 6: DP (printf ("Max. Cas Latencies (DDR): ERROR !!!\n")); dimmInfo-> maxClSupported_DDR = DDR_CL_FAULT; hang (); break; case 5: DP (printf ("Max. Cas Latencies (DDR): 3.5 clk's\n")); dimmInfo-> maxClSupported_DDR = DDR_CL_3_5; break; case 4: DP (printf ("Max. Cas Latencies (DDR): 3 clk's \n")); dimmInfo-> maxClSupported_DDR = DDR_CL_3; break; case 3: DP (printf ("Max. Cas Latencies (DDR): 2.5 clk's \n")); dimmInfo-> maxClSupported_DDR = DDR_CL_2_5; break; case 2: DP (printf ("Max. Cas Latencies (DDR): 2 clk's \n")); dimmInfo-> maxClSupported_DDR = DDR_CL_2; break; case 1: DP (printf ("Max. Cas Latencies (DDR): 1.5 clk's \n")); dimmInfo-> maxClSupported_DDR = DDR_CL_1_5; break; } dimmInfo-> maxCASlatencySupported_LoP = 1 + (int) (5 * j / 10); if (((5 * j) % 10) != 0) dimmInfo-> maxCASlatencySupported_RoP = 5; else dimmInfo-> maxCASlatencySupported_RoP = 0; DP (printf ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", dimmInfo-> maxCASlatencySupported_LoP, dimmInfo-> maxCASlatencySupported_RoP)); break; case SDRAM: /* CAS latency 1, 2, 3, 4, 5, 6, 7 */ dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */ DP (printf ("Max. Cas Latencies (SD): %d\n", dimmInfo-> maxClSupported_SD)); dimmInfo-> maxCASlatencySupported_LoP = j; dimmInfo-> maxCASlatencySupported_RoP = 0; DP (printf ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", dimmInfo-> maxCASlatencySupported_LoP, dimmInfo-> maxCASlatencySupported_RoP)); break; } break; } } break;/*------------------------------------------------------------------------------------------------------------------------------*/ case 21: /* Buffered Address And Control Inputs */ DP (printf ("\nModul Attributes (SPD Byte 21): \n")); dimmInfo->bufferedAddrAndControlInputs = data[i] & BIT0; dimmInfo->registeredAddrAndControlInputs = (data[i] & BIT1) >> 1; dimmInfo->onCardPLL = (data[i] & BIT2) >> 2; dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3; dimmInfo->registeredDQMBinputs = (data[i] & BIT4) >> 4; dimmInfo->differentialClockInput = (data[i] & BIT5) >> 5; dimmInfo->redundantRowAddressing = (data[i] & BIT6) >> 6;#ifdef DEBUG if (dimmInfo->bufferedAddrAndControlInputs == 1) DP (printf (" - Buffered Address/Control Input: Yes \n")); else DP (printf (" - Buffered Address/Control Input: No \n")); if (dimmInfo->registeredAddrAndControlInputs == 1) DP (printf (" - Registered Address/Control Input: Yes \n")); else DP (printf (" - Registered Address/Control Input: No \n")); if (dimmInfo->onCardPLL == 1) DP (printf (" - On-Card PLL (clock): Yes \n")); else DP (printf (" - On-Card PLL (clock): No \n")); if (dimmInfo->bufferedDQMBinputs == 1) DP (printf (" - Bufferd DQMB Inputs: Yes \n")); else DP (printf (" - Bufferd DQMB Inputs: No \n")); if (dimmInfo->registeredDQMBinputs == 1) DP (printf (" - Registered DQMB Inputs: Yes \n")); else DP (printf (" - Registered DQMB Inputs: No \n")); if (dimmInfo->differentialClockInput == 1) DP (printf (" - Differential Clock Input: Yes \n")); else DP (printf (" - Differential Clock Input: No \n")); if (dimmInfo->redundantRowAddressing == 1) DP (printf (" - redundant Row Addressing: Yes \n")); else DP (printf (" - redundant Row Addressing: No \n"));#endif break;/*------------------------------------------------------------------------------------------------------------------------------*/?? 快捷鍵說明
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