int galbrg_set_baudrate (int channel, int rate){	DECLARE_GLOBAL_DATA_PTR;	int clock;	galbrg_disable (channel);	/*ok */#ifdef ZUMA_NTL	/* from tclk */	clock = (CFG_TCLK / (16 * rate)) - 1;#else	clock = (CFG_TCLK / (16 * rate)) - 1;#endif	galbrg_set_CDV (channel, clock);	/* set timer Reg. for BRG */	galbrg_enable (channel);	gd->baudrate = rate;	return 0;}/* ------------------------------------------------------------------ *//* Below are all the private functions that no one else needs */static int galbrg_set_CDV (int channel, int value){	unsigned int temp;	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));	temp &= 0xFFFF0000;	temp |= (value & 0x0000FFFF);	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);	return 0;}static int galbrg_enable (int channel){	unsigned int temp;	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));	temp |= 0x00010000;	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);	return 0;}static int galbrg_disable (int channel){	unsigned int temp;	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));	temp &= 0xFFFEFFFF;	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);	return 0;}static int galbrg_set_clksrc (int channel, int value){	unsigned int temp;	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));	temp &= 0xFFC3FFFF;	/* Bit 18 - 21 (MV 64260 18-22) */	temp |= (value << 18);	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);	return 0;}static int galbrg_set_CUV (int channel, int value){	/* set CountUpValue */	GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value);	return 0;}#if 0static int galbrg_reset (int channel){	unsigned int temp;	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));	temp |= 0x20000;	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);	return 0;}#endifstatic int galsdma_set_RFT (int channel){	unsigned int temp;	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));	temp |= 0x00000001;	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),		      temp);	return 0;}static int galsdma_set_SFM (int channel){	unsigned int temp;	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));	temp |= 0x00000002;	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),		      temp);	return 0;}static int galsdma_set_rxle (int channel){	unsigned int temp;	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));	temp |= 0x00000040;	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),		      temp);	return 0;}static int galsdma_set_txle (int channel){	unsigned int temp;	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));	temp |= 0x00000080;	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),		      temp);	return 0;}static int galsdma_set_RC (int channel, unsigned int value){	unsigned int temp;	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));	temp &= ~0x0000003c;	temp |= (value << 2);	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),		      temp);	return 0;}static int galsdma_set_burstsize (int channel, unsigned int value){	unsigned int temp;	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));	temp &= 0xFFFFCFFF;	switch (value) {	case 8:		GT_REG_WRITE (GALSDMA_0_CONF_REG +			      (channel * GALSDMA_REG_DIFF),			      (temp | (0x3 << 12)));		break;	case 4:		GT_REG_WRITE (GALSDMA_0_CONF_REG +			      (channel * GALSDMA_REG_DIFF),			      (temp | (0x2 << 12)));		break;	case 2:		GT_REG_WRITE (GALSDMA_0_CONF_REG +			      (channel * GALSDMA_REG_DIFF),			      (temp | (0x1 << 12)));		break;	case 1:		GT_REG_WRITE (GALSDMA_0_CONF_REG +			      (channel * GALSDMA_REG_DIFF),			      (temp | (0x0 << 12)));		break;	default:		return -1;		break;	}	return 0;}static int galmpsc_connect (int channel, int connect){	unsigned int temp;	temp = GTREGREAD (GALMPSC_ROUTING_REGISTER);	if ((channel == 0) && connect)		temp &= ~0x00000007;	else if ((channel == 1) && connect)		temp &= ~(0x00000007 << 6);	else if ((channel == 0) && !connect)		temp |= 0x00000007;	else		temp |= (0x00000007 << 6);	/* Just in case... */	temp &= 0x3fffffff;	GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp);	return 0;}static int galmpsc_route_rx_clock (int channel, int brg){	unsigned int temp;	temp = GTREGREAD (GALMPSC_RxC_ROUTE);	if (channel == 0) {		temp &= ~0x0000000F;		temp |= brg;	} else {		temp &= ~0x00000F00;		temp |= (brg << 8);	}	GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp);	return 0;}static int galmpsc_route_tx_clock (int channel, int brg){	unsigned int temp;	temp = GTREGREAD (GALMPSC_TxC_ROUTE);	if (channel == 0) {		temp &= ~0x0000000F;		temp |= brg;	} else {		temp &= ~0x00000F00;		temp |= (brg << 8);	}	GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp);	return 0;}static int galmpsc_write_config_regs (int mpsc, int mode){	if (mode == GALMPSC_UART) {		/* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */		GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP),			      0x000004c4);		/* Main config reg High (32x Rx/Tx clock mode, width=8bits */		GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP),			      0x024003f8);		/*        22 2222 1111 */		/*        54 3210 9876 */		/* 0000 0010 0000 0000 */		/*       1 */		/*       098 7654 3210 */		/* 0000 0011 1111 1000 */	} else		return -1;	return 0;}static int galmpsc_config_channel_regs (int mpsc){	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0);	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0);	GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1);	GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0);	GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0);	GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0);	GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0);	GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0);	GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0);	GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0);	galmpsc_set_brkcnt (mpsc, 0x3);	galmpsc_set_tcschar (mpsc, 0xab);	return 0;}static int galmpsc_set_brkcnt (int mpsc, int value){	unsigned int temp;	temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));	temp &= 0x0000FFFF;	temp |= (value << 16);	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);	return 0;}static int galmpsc_set_tcschar (int mpsc, int value){	unsigned int temp;	temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));	temp &= 0xFFFF0000;	temp |= value;	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);	return 0;}static int galmpsc_set_char_length (int mpsc, int value){	unsigned int temp;	temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));	temp &= 0xFFFFCFFF;	temp |= (value << 12);	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);	return 0;}static int galmpsc_set_stop_bit_length (int mpsc, int value){	unsigned int temp;	temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));	temp &= 0xFFFFBFFF;	temp |= (value << 14);	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);	return 0;}static int galmpsc_set_parity (int mpsc, int value){	unsigned int temp;	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));	if (value != -1) {		temp &= 0xFFF3FFF3;		temp |= ((value << 18) | (value << 2));		temp |= ((value << 17) | (value << 1));	} else {		temp &= 0xFFF1FFF1;	}	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);	return 0;}static int galmpsc_enter_hunt (int mpsc){	int temp;	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));	temp |= 0x80000000;	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);	while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) &	       MPSC_ENTER_HUNT) {		udelay (1);	}	return 0;}static int galmpsc_shutdown (int mpsc){	unsigned int temp;	/* cause RX abort (clears RX) */	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));	temp |= MPSC_RX_ABORT | MPSC_TX_ABORT;	temp &= ~MPSC_ENTER_HUNT;	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);	GT_REG_WRITE (GALSDMA_0_COM_REG, 0);	GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT);	/* shut down the MPSC */	GT_REG_WRITE (GALMPSC_MCONF_LOW, 0);	GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0);	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0);	udelay (100);	/* shut down the sdma engines. */	/* reset config to default */	GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc);	udelay (100);	/* clear the SDMA current and first TX and RX pointers */	GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0);	GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0);	GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0);	udelay (100);	return 0;}static void galsdma_enable_rx (void){	int temp;	/* Enable RX processing */	temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));	temp |= RX_ENABLE;	GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);	galmpsc_enter_hunt (CHANNEL);}static int galmpsc_set_snoop (int mpsc, int value){	int reg =		mpsc ? MPSC_1_ADDRESS_CONTROL_LOW :		MPSC_0_ADDRESS_CONTROL_LOW;	int temp = GTREGREAD (reg);	if (value)		temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30);	else		temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30));	GT_REG_WRITE (reg, temp);	return 0;}/******************************************************************************** galsdma_set_mem_space - Set MV64360 IDMA memory decoding map.** DESCRIPTION:*       the MV64360 SDMA has its own address decoding map that is de-coupled*       from the CPU interface address decoding windows. The SDMA channels*       share four address windows. Each region can be individually configured*       by this function by associating it to a target interface and setting*       base and size values.**      NOTE!!!*       The size must be in 64Kbyte granularity.*       The base address must be aligned to the size.*       The size must be a series of 1s followed by a series of zeros** OUTPUT:*       None.** RETURN:*       True for success, false otherwise.********************************************************************************/static int galsdma_set_mem_space (unsigned int memSpace,				  unsigned int memSpaceTarget,				  unsigned int memSpaceAttr,				  unsigned int baseAddress, unsigned int size){	unsigned int temp;	if (size == 0) {		GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG,				   1 << memSpace);		return true;	}	/* The base address must be aligned to the size.  */	if (baseAddress % size != 0) {		return false;	}	if (size < 0x10000) {		return false;	}	/* Align size and base to 64K */	baseAddress &= 0xffff0000;	size &= 0xffff0000;	temp = size >> 16;	/* Checking that the size is a sequence of '1' followed by a	   sequence of '0' starting from LSB to MSB. */	while ((temp > 0) && (temp & 0x1)) {		temp = temp >> 1;	}	if (temp != 0) {		GT_REG_WRITE (MV64360_CUNIT_BASE_ADDR_REG0 + memSpace * 8,			      (baseAddress | memSpaceTarget | memSpaceAttr));		GT_REG_WRITE ((MV64360_CUNIT_SIZE0 + memSpace * 8),			      (size - 1) & 0xffff0000);		GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG,				   1 << memSpace);	} else {		/* An invalid size was specified */		return false;	}	return true;}