?? clkscan3.fit.eqn
字號:
E1_min[2] = DFFEAS(E1_min[2]_lut_out, GLOBAL(E1_min_clk), GLOBAL(D2_signal), , , , , !E1L32, );
--S32L1 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[1]~COUT at LC_X35_Y13_N6
--operation mode is arithmetic
S32L1_cout_0 = E1_min[2];
S32L1 = CARRY(S32L1_cout_0);
--S32L2 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[1]~COUTCOUT1 at LC_X35_Y13_N6
--operation mode is arithmetic
S32L2_cout_1 = E1_min[2];
S32L2 = CARRY(S32L2_cout_1);
--S42L4 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~46 at LC_X31_Y18_N6
--operation mode is arithmetic
S42L4 = S42L41 $ (!M6L02 & !M6L91);
--S42L5 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~48 at LC_X31_Y18_N6
--operation mode is arithmetic
S42L5_cout_0 = !M6L02 & !M6L91 & !S42L41;
S42L5 = CARRY(S42L5_cout_0);
--S42L6 is clkscan:inst7|lpm_divide:mod_rtl_4|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~48COUT1 at LC_X31_Y18_N6
--operation mode is arithmetic
S42L6_cout_1 = !M6L02 & !M6L91 & !S42L51;
S42L6 = CARRY(S42L6_cout_1);
--F1L9 is clkscan:inst7|Select~1306 at LC_X31_Y18_N4
--operation mode is normal
F1L9 = S42L3 & (S42L4) # !S42L3 & (S32L3 $ E1_min[2]);
--F1L01 is clkscan:inst7|Select~1307 at LC_X30_Y17_N7
--operation mode is normal
F1_scan_en[5]_qfbk = F1_scan_en[5];
F1L01 = !S02L3 & F1_scan_en[5]_qfbk;
--F1_scan_en[5] is clkscan:inst7|scan_en[5] at LC_X30_Y17_N7
--operation mode is normal
F1_scan_en[5] = DFFEAS(F1L01, !GLOBAL(C1_clkout), GLOBAL(D2_signal), , , F1_scan_en[4], , , VCC);
--S91L3 is clkscan:inst7|lpm_divide:mod_rtl_2|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~41 at LC_X29_Y17_N9
--operation mode is normal
S91L3 = !S91L8;
--E1_hour[2] is timer:inst6|hour[2] at LC_X27_Y17_N2
--operation mode is arithmetic
E1_hour[2]_lut_out = E1L31;
E1_hour[2] = DFFEAS(E1_hour[2]_lut_out, GLOBAL(E1_h_clk), GLOBAL(D2_signal), , , , , , );
--S91L1 is clkscan:inst7|lpm_divide:mod_rtl_2|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[1]~COUT at LC_X27_Y17_N2
--operation mode is arithmetic
S91L1_cout_0 = E1_hour[2];
S91L1 = CARRY(S91L1_cout_0);
--S91L2 is clkscan:inst7|lpm_divide:mod_rtl_2|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[1]~COUTCOUT1 at LC_X27_Y17_N2
--operation mode is arithmetic
S91L2_cout_1 = E1_hour[2];
S91L2 = CARRY(S91L2_cout_1);
--S6L5 is clkscan:inst7|lpm_divide:div_rtl_3|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~41 at LC_X35_Y14_N9
--operation mode is normal
S6L5 = !S6L7;
--S01L5 is clkscan:inst7|lpm_divide:div_rtl_5|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~41 at LC_X31_Y15_N4
--operation mode is normal
S01L5 = !S01L7;
--F1L11 is clkscan:inst7|Select~1308 at LC_X30_Y19_N4
--operation mode is normal
F1_scan_en[4]_qfbk = F1_scan_en[4];
F1L11 = F1_scan_en[1] & (F1_scan_en[4]_qfbk & S6L5) # !F1_scan_en[1] & (S01L5 # F1_scan_en[4]_qfbk & S6L5);
--F1_scan_en[4] is clkscan:inst7|scan_en[4] at LC_X30_Y19_N4
--operation mode is normal
F1_scan_en[4] = DFFEAS(F1L11, !GLOBAL(C1_clkout), GLOBAL(D2_signal), , , F1_scan_en[2], , , VCC);
--S61L6 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~46 at LC_X29_Y18_N1
--operation mode is arithmetic
S61L6 = S61L61 $ (!M4L02 & !M4L91);
--S61L7 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~48 at LC_X29_Y18_N1
--operation mode is arithmetic
S61L7_cout_0 = !M4L02 & !M4L91 & !S61L61;
S61L7 = CARRY(S61L7_cout_0);
--S61L8 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~48COUT1 at LC_X29_Y18_N1
--operation mode is arithmetic
S61L8_cout_1 = !M4L02 & !M4L91 & !S61L71;
S61L8 = CARRY(S61L8_cout_1);
--S51L5 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~41 at LC_X30_Y14_N9
--operation mode is normal
S51L5 = !S51L01;
--S51_add_sub_cella[1] is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[1] at LC_X32_Y19_N3
--operation mode is arithmetic
S51_add_sub_cella[1] = E1_sec[2];
--S51L3 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[1]~COUT at LC_X32_Y19_N3
--operation mode is arithmetic
S51L3_cout_0 = E1_sec[2];
S51L3 = CARRY(S51L3_cout_0);
--S51L4 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[1]~COUTCOUT1 at LC_X32_Y19_N3
--operation mode is arithmetic
S51L4_cout_1 = E1_sec[2];
S51L4 = CARRY(S51L4_cout_1);
--M4L02 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[31]~18 at LC_X30_Y14_N1
--operation mode is normal
M4L02 = !S51_add_sub_cella[1] & (S51L5);
--E1_sec[2] is timer:inst6|sec[2] at LC_X28_Y13_N2
--operation mode is arithmetic
E1_sec[2]_lut_out = E1_sec[2] $ (!E1L08);
E1_sec[2] = DFFEAS(E1_sec[2]_lut_out, GLOBAL(B1_clkout), GLOBAL(D2_signal), , , , , E1L99, );
--E1L38 is timer:inst6|sec[2]~113 at LC_X28_Y13_N2
--operation mode is arithmetic
E1L38_cout_0 = E1_sec[2] & (!E1L08);
E1L38 = CARRY(E1L38_cout_0);
--E1L48 is timer:inst6|sec[2]~113COUT1_140 at LC_X28_Y13_N2
--operation mode is arithmetic
E1L48_cout_1 = E1_sec[2] & (!E1L18);
E1L48 = CARRY(E1L48_cout_1);
--M4L91 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[31]~13 at LC_X29_Y14_N4
--operation mode is normal
M4L91 = E1_sec[2] & (!S51L5);
--F1L21 is clkscan:inst7|Select~1309 at LC_X29_Y18_N9
--operation mode is normal
F1L21 = S61L5 & S61L6 # !S61L5 & (M4L91 # M4L02);
--F1L31 is clkscan:inst7|Select~1310 at LC_X30_Y19_N2
--operation mode is normal
F1L31 = F1L11 # F1L21 & F1_scan_en[8];
--F1L41 is clkscan:inst7|Select~1311 at LC_X30_Y17_N8
--operation mode is normal
F1L41 = F1L31 # F1L01 & (S91L3 $ E1_hour[2]);
--S5L3 is clkscan:inst7|lpm_divide:div_rtl_3|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~41 at LC_X32_Y15_N4
--operation mode is normal
S5L3 = !S5L5;
--S9L5 is clkscan:inst7|lpm_divide:div_rtl_5|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~41 at LC_X29_Y15_N4
--operation mode is normal
S9L5 = !S9L7;
--F1L51 is clkscan:inst7|Select~1313 at LC_X32_Y17_N9
--operation mode is normal
F1L51 = F1_scan_en[1] & F1_scan_en[4] & (S5L3) # !F1_scan_en[1] & (S9L5 # F1_scan_en[4] & S5L3);
--S81L3 is clkscan:inst7|lpm_divide:mod_rtl_2|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~41 at LC_X28_Y16_N4
--operation mode is normal
S81L3 = !S81L5;
--E1_hour[3] is timer:inst6|hour[3] at LC_X27_Y17_N0
--operation mode is arithmetic
E1_hour[3]_lut_out = E1L86;
E1_hour[3] = DFFEAS(E1_hour[3]_lut_out, GLOBAL(E1_h_clk), GLOBAL(D2_signal), , , , , !E1L62, );
--S81L1 is clkscan:inst7|lpm_divide:mod_rtl_2|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[1]~COUT at LC_X27_Y17_N0
--operation mode is arithmetic
S81L1_cout_0 = E1_hour[3];
S81L1 = CARRY(S81L1_cout_0);
--S81L2 is clkscan:inst7|lpm_divide:mod_rtl_2|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[1]~COUTCOUT1 at LC_X27_Y17_N0
--operation mode is arithmetic
S81L2_cout_1 = E1_hour[3];
S81L2 = CARRY(S81L2_cout_1);
--M5L22 is clkscan:inst7|lpm_divide:mod_rtl_2|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[32]~609 at LC_X30_Y18_N7
--operation mode is normal
M5L22 = !S91L3 & (S81L3 $ (E1_hour[3]));
--S91L4 is clkscan:inst7|lpm_divide:mod_rtl_2|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~46 at LC_X29_Y17_N6
--operation mode is arithmetic
S91L4 = S91L11 $ (!M5L31 & !M5L41);
--S91L5 is clkscan:inst7|lpm_divide:mod_rtl_2|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~48 at LC_X29_Y17_N6
--operation mode is arithmetic
S91L5_cout_0 = !M5L31 & !M5L41 & !S91L11;
S91L5 = CARRY(S91L5_cout_0);
--S91L6 is clkscan:inst7|lpm_divide:mod_rtl_2|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~48COUT1 at LC_X29_Y17_N6
--operation mode is arithmetic
S91L6_cout_1 = !M5L31 & !M5L41 & !S91L21;
S91L6 = CARRY(S91L6_cout_1);
--M5L12 is clkscan:inst7|lpm_divide:mod_rtl_2|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[32]~17 at LC_X29_Y17_N0
--operation mode is normal
M5L12 = S91L3 & S91L4;
--F1L61 is clkscan:inst7|Select~1314 at LC_X30_Y18_N8
--operation mode is normal
F1L61 = F1L51 # F1L01 & (M5L12 # M5L22);
--E1_sec[3] is timer:inst6|sec[3] at LC_X28_Y13_N3
--operation mode is arithmetic
E1_sec[3]_lut_out = E1_sec[3] $ E1L38;
E1_sec[3] = DFFEAS(E1_sec[3]_lut_out, GLOBAL(B1_clkout), GLOBAL(D2_signal), , , , , E1L99, );
--E1L68 is timer:inst6|sec[3]~117 at LC_X28_Y13_N3
--operation mode is arithmetic
E1L68_cout_0 = !E1L38 # !E1_sec[3];
E1L68 = CARRY(E1L68_cout_0);
--E1L78 is timer:inst6|sec[3]~117COUT1 at LC_X28_Y13_N3
--operation mode is arithmetic
E1L78_cout_1 = !E1L48 # !E1_sec[3];
E1L78 = CARRY(E1L78_cout_1);
--S41L5 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~41 at LC_X29_Y14_N9
--operation mode is normal
S41L5 = !S41L7;
--S41_add_sub_cella[1] is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[1] at LC_X38_Y13_N5
--operation mode is arithmetic
S41_add_sub_cella[1] = E1_sec[3];
--S41L3 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[1]~COUT at LC_X38_Y13_N5
--operation mode is arithmetic
S41L3_cout_0 = E1_sec[3];
S41L3 = CARRY(S41L3_cout_0);
--S41L4 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[1]~COUTCOUT1 at LC_X38_Y13_N5
--operation mode is arithmetic
S41L4_cout_1 = E1_sec[3];
S41L4 = CARRY(S41L4_cout_1);
--M4L22 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[32]~609 at LC_X29_Y14_N0
--operation mode is normal
M4L22 = !S51L5 & (S41L5 & (!S41_add_sub_cella[1]) # !S41L5 & E1_sec[3]);
--S51L6 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~46 at LC_X30_Y14_N6
--operation mode is arithmetic
S51L6 = S51L31 $ (!M4L41 & !M4L31);
--S51L7 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~48 at LC_X30_Y14_N6
--operation mode is arithmetic
S51L7_cout_0 = !M4L41 & !M4L31 & !S51L31;
S51L7 = CARRY(S51L7_cout_0);
--S51L8 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~48COUT1 at LC_X30_Y14_N6
--operation mode is arithmetic
S51L8_cout_1 = !M4L41 & !M4L31 & !S51L41;
S51L8 = CARRY(S51L8_cout_1);
--M4L12 is clkscan:inst7|lpm_divide:mod_rtl_0|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[32]~17 at LC_X29_Y18_N7
--operation mode is normal
M4L12 = S51L5 & (S51L6);
--F1L71 is clkscan:inst7|Select~1315 at LC_X29_Y18_N6
--operation mode is normal
F1_scan_en[8]_qfbk = F1_scan_en[8];
F1L71 = !S61L5 & F1_scan_en[8]_qfbk & (M4L12 # M4L22);
--F1_scan_en[8] is clkscan:inst7|scan_en[8] at LC_X29_Y18_N6
--operation mode is normal
F1_scan_en[8] = DFFEAS(F1L71, !GLOBAL(C1_clkout), GLOBAL(D2_signal), , , F1_scan_en[7], , , VCC);
--S02L7 is clkscan:inst7|lpm_divide:mod_rtl_2|lpm_divide_ndf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~51 at LC_X30_Y17_N2
--operation mode is arithmetic
S02L7 = S02L5 $ (!M5L22 & !M5L12);
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