module timer(clk,reset,start,sec,min,hour,day);
  input clk,reset,start;   // Tclk=0.25s
  output[7:0] sec,min,hour;
  output day;
  reg[7:0] sec,min,hour;
  reg min_clk,h_clk,day;
  reg started;                    // 中間變量，用于將start脈沖信號轉變為電平信號
 
  always @(negedge reset or negedge start) //（1）將startn脈沖信號轉變為電平信號 
	begin
		if(!reset)started=0;
		else started=1;		
	end
	
  always@(posedge clk or negedge reset)  //（2）秒計時
	begin
		if(!reset)begin sec=0;min_clk=0;end
		else if(started)
		begin
			if(sec==59)
				begin
					min_clk=1;
					sec=0;
				end
			else
				begin
					min_clk=0;
					sec=sec+1;
				end
		end
		else begin sec=0;min_clk=0;end			
	end
	
  always @(posedge min_clk or negedge reset)//（3）分計時
	begin
		if(!reset)
			begin
			min=0;
			end
		else
			begin
				if(min==59)
					begin
					h_clk=1;
					min=0;
					end
				else
					begin
					h_clk=0;
					min=min+1;
					end
			end					
	end
	
  always @(posedge h_clk or negedge reset)//（4）小時計時
	begin
		if(!reset)
			begin
			hour=0;
			end
		else
			begin
				if(hour==23)
					begin
					day=1;
					hour=0;
					end
				else
					begin
					day=0;
					hour=hour+1;
					end
			end					
	end

endmodule