library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity fsk is
port(clock: in std_logic; 
     a:in std_logic_vector(2 downto 0);     ----輸入控制信號，3位用來選擇M序列長度
     b:in std_logic_vector(1 downto 0);      ----輸入控制信號，2位用來選擇M序列反饋系數
     load:in std_logic; ----m序列控制信號
     d:out std_logic_vector (7 downto 0); 
     load_clock:buffer std_logic; 
      load_clock1:buffer std_logic; 
     code,coderate: buffer std_logic;
     jump_high:buffer std_logic;   
     jump_low:buffer std_logic);  
end fsk;

architecture ab of fsk is
 signal  q1: std_logic;
signal c0,c1,c2,c3,c4,c5,c6,c7:std_logic;                                                   ---所以采用雙相碼分別表示－1，1，0

signal count64:std_logic_vector (7 downto 0);
signal count32: std_logic_vector (4 downto 0);
signal count: std_logic_vector (2 downto 0);
signal count1: std_logic_vector (1 downto 0);
signal count20:std_logic_vector (3 downto 0);
signal sinclk: std_logic;
--signal sinclk1: std_logic;
signal temp:std_logic;
begin
process(clock) --100khz分頻10得到load_clock為10khz
begin
  if(clock'event and clock='1') then
 if(count="100") then --記錄10個周期
    count<="000";
   load_clock<=not load_clock;
   else count<=count+'1';
if(count20="1001") then --記錄20個周期
    count20<="0000";
   load_clock1<=not load_clock1;
   else count20<=count20+'1';
end if;
  end if;
  end if;
end process;

--process(load_clock1)
--begin
 --if(load_clock1'event and load_clock1='1') then
--if(count1="11") then --4
  --  count1<="00";
   -- load_clock1<=not load_clock1;
  -- else count1<=count1+'1';
  -- end if;
 -- end if;
--end process;


process(load_clock1)  --load_clock分頻64得到0.5KHz碼元速率
begin
 if(load_clock1'event and load_clock1='1') then
   if(count32="11111") then --記錄32個周期
    count32<="00000";
    coderate<=not coderate;
   else count32<=count32+'1';
   end if;
  end if;
end process;

process( coderate) ---m序列進程
begin
if  coderate'event and  coderate='1' then   -----二分頻時鐘信號上升沿
case a is
when "000"  =>  ---a為000，010，001分別表示M序列級數為0，1，2此時設置為復位
q1<='0';
when "001"  =>  
q1<='0';
when "010" =>     ---a為010代表M序列級數為2時此時序列長度為3，反饋系數為7=111 
if load='1' or ((  c1 or c0)='0') then
             -----load 優先控制 避免全零

c1<='1';
c0<='1';
q1<=c1;
else

c0<=c1 xor c0  ;  ------設置反饋方式
c1<=c0;
q1<=c1;
end if;
when "011" =>     ---a為011代表M序列級數為3時此時序列長度為7，反饋系數為13=1011 
if load='1' or ((  c2 or c1 or c0)='0')   then
             -----load 優先控制 避免全零
c2<='1';
c1<='1';
c0<='1';
q1<=c2;

else

c0<=c1 xor c2 ;  ------設置反饋方式
c2<=c1;
c1<=c0;
q1<=c2;
end if;
when "100" =>       ---a為100代表M序列級數為4時此時序列長度為15，反饋系數為23=10011  
if load='1' or (( c3 or c2 or c1 or c0)='0') then
             -----load 優先控制 避免全零

c3<='0';
c2<='0';
c1<='0';
c0<='1';
q1<=c4;
else
c0<=c2 xor c3 ;  ------設置反饋方式
c3<=c2;
c2<=c1;
c1<=c0;
q1<=c3;
end if;
when "101"=>     ---a為101代表M序列級數為5時此時序列長度為31，反饋系數為45,67,75  
case b is
when  "00" =>   -----b為00時,則設定此時無反饋系數
q1<='0';
when  "01" =>   -----b為01時,則設定此反饋系數為45=100101

if load='1' or (( c4 or c3 or c2 or c1 or c0)='0') then
             -----load 優先控制 避免全零
c4<='0';
c3<='0';
c2<='0';
c1<='1';
c0<='1';
q1<=c4;
else
c0<=c4  xor c2;  ------設置反饋方式
c4<=c3;
c3<=c2;
c2<=c1;
c1<=c0;
q1<=c4;
end if;
when "10" =>   -----b為10時,則設定此反饋系數為67=110111
if load='1' or (( c4 or c3 or c2 or c1 or c0)='0') then
             -----load 優先控制 避免全零
c4<='0';
c3<='0';
c2<='0';
c1<='1';
c0<='1';
q1<=c4;
else
c0<=c4 xor c3 xor c2 xor c0 ;------設置反饋方式
c4<=c3;
c3<=c2;
c2<=c1;
c1<=c0;
q1<=c4;
end if;
when "11" =>   -----b為11時,則設定此反饋系數為75=111101
if load='1' or (( c4 or c3 or c2 or c1 or c0)='0') then
             -----load 優先控制 避免全零
c4<='0';
c3<='0';
c2<='0';
c1<='1';
c0<='1';
q1<=c4;
else
c0<=c0 xor c1 xor c2 xor c4 ;  ------設置反饋方式
c4<=c3;
c3<=c2;
c2<=c1;
c1<=c0;
q1<=c4;
end if;
when others =>
q1<='0';
end case;

when "110"=>     ---a為110代表M序列級數為6時此時序列長度為63，反饋系數為103,147,155
case  b  is
when  "00" =>   -----b為00時,則設定此時無反饋系數
q1<='0';

when "01" =>      ----b為00或01時,則設定此反饋系數為103=1000011

if load='1' or ((  c5 or c4 or c3 or c2 or c1 or c0)='0') then
             -----load 優先控制 避免全零

c5<='0';
c4<='0';
c3<='0';
c2<='0';
c1<='1';
c0<='1';
q1<=c5;
else
c0<=c5  xor c4 ;  ------設置反饋方式
c5<=c4;
c4<=c3;
c3<=c2;
c2<=c1;
c1<=c0;
q1<=c5;
end if;
when "10" =>   -----b為10時,則設定此反饋系數為147=1100111
if load='1' or (( c5 or c4 or c3 or c2 or c1 or c0)='0') then
             -----load 優先控制 避免全零

c5<='0';
c4<='0';
c3<='0';
c2<='0';
c1<='1';
c0<='1';
q1<=c5;
else
c0<=c5 xor c4 xor c1 xor c0 ;  ------設置反饋方式
c5<=c4;
c4<=c3;
c3<=c2;
c2<=c1;
c1<=c0;
q1<=c5;
end if;
when "11" =>   -----b為11時,則設定此反饋系數為155=1101101
if load='1' or (( c5 or c4 or c3 or c2 or c1 or c0)='0') then
             -----load 優先控制 避免全零

c5<='0';
c4<='0';
c3<='0';
c2<='0';
c1<='1';
c0<='1';
q1<=c5;
else
c0<=c5 xor c4 xor c2 xor c1 ;  ------設置反饋方式
c5<=c4;
c4<=c3;
c3<=c2;
c2<=c1;
c1<=c0;
q1<=c5;
end if;
when others =>
q1<='0';
end case;
when "111"=>     ---a為111代表M序列級數為7時此時序列長度為127，反饋系數為203,211,217,235,277,313,325,345,367
                 ----此處選擇反饋系數203，211，217，235為例
case b is
when "00" =>   -----b為00時,則設定此反饋系數為203=10000011
if load='1' or ((c6 or c5 or c4 or c3 or c2 or c1 or c0)='0') then
             -----load 優先控制 避免全零

c6<='0';
c5<='0';
c4<='0';
c3<='0';
c2<='0';
c1<='1';
c0<='1';
q1<=c6;
else
c0<=c6 xor c0 ;  ------設置反饋方式
c6<=c5;
c5<=c4;
c4<=c3;
c3<=c2;
c2<=c1;
c1<=c0;
q1<=c6;
end if;
when "01" =>   -----b為01時,則設定此反饋系數為211=10001001
if load='1' or (( c6 or c5 or c4 or c3 or c2 or c1 or c0)='0') then
             -----load 優先控制 避免全零
c6<='0';
c5<='0';
c4<='0';
c3<='0';
c2<='0';
c1<='1';
c0<='1';
q1<=c6;
else
c0<=c6 xor  c2 ;  ------設置反饋方式
c6<=c5;
c5<=c4;
c4<=c3;
c3<=c2;
c2<=c1;
c1<=c0;
q1<=c6;
end if;
when "10" =>   -----b為10時,則設定此反饋系數為217=10001111
if load='1' or ((c6 or c5 or c4 or c3 or c2 or c1 or c0)='0') then
             -----load 優先控制 避免全零
c6<='0';
c5<='0';
c4<='0';
c3<='0';
c2<='0';
c1<='1';
c0<='1';
q1<=c6;
else
c0<=c6 xor c2 xor c1 xor c0 ;  ------設置反饋方式
c6<=c5;
c5<=c4;
c4<=c3;
c3<=c2;
c2<=c1;
c1<=c0;
q1<=c6;
end if;
when "11" =>   -----b為10時,則設定此反饋系數為235=10011101
if load='1' or (( c6 or c5 or c4 or c3 or c2 or c1 or c0)='0') then
             -----load 優先控制 避免全零
c6<='0';
c5<='0';
c4<='0';
c3<='0';
c2<='0';
c1<='1';
c0<='1';
q1<=c6;
else

c0<=c6 xor c3 xor c2 xor c1;  ------設置反饋方式

c6<=c5;
c5<=c4;
c4<=c3;
c3<=c2;
c2<=c1;
c1<=c0;
q1<=c6;
end if;
when others=>
q1<='0';
end case;
when others=>
q1<='0';
end case;
end if;
end  process;
code<=q1;
sinclk<=load_clock; 
--sinclk1<=load_clock1;   
jump_high<=(not temp) and code; --0到1跳變
jump_low<=(not code) and temp;  --1到0跳變

 
process(sinclk)
begin
 if(sinclk'event and sinclk='1') then
         temp<=code;     
   if((jump_high='1')or(count64="00111111")or (jump_low='1')) 
               then count64<="00000000"; 
        elsif(temp='0')then 
             if(count1="01")then
                  count1<="00";
          count64<=count64+'1';
                else count1<=count1+'1';
          --end if;

            if (temp='1')then 
               count64<=count64+'1';   
  end if;         
 end if;
   end if;          
 end if;           
         
--end if;
  -- end if;
    
--if(sinclk1'event and sinclk1='1') then
   --if((jump_low='1')or(count64="00111111")) 
              -- then count64<="00000000"; 
        --elsif(temp='1') then 
          --count64<=count64+'1';   
  -- end if;      
   --end if;
end process;


process(count64)
begin
 case count64 is
when "00000000"=> d<="00000000"  ;when "00000001"=> d<="00000001"  ;
when "00000010"=> d<="00000100"  ;when "00000011"=> d<="00001000"  ;
when "00000100"=> d<="00001101"  ;when "00000101"=> d<="00010011"  ;
when "00000110"=> d<="00011010"  ;when "00000111"=> d<="00100010"  ;
when "00001000"=> d<="00101011"  ;when "00001001"=> d<="00110101"  ;
when "00001010"=> d<="01000000"  ;when "00001011"=> d<="01001011"  ;
when "00001100"=> d<="01010111"  ; when "00001101"=> d<="01100011"  ;
when "00001110"=> d<="01110000"  ;when "00001111"=> d<="01111100"  ;
when "00010000"=> d<="10001001"  ; when "00010001"=> d<="10010110"  ;
when "00010010"=> d<="10100010"  ;when "00010011"=> d<="10101110"  ;
when "00010100"=> d<="10111010"  ; when "00010101"=> d<="11000101"  ;
when "00010110"=> d<="11001111"  ;when "00010111"=> d<="11011001"  ;
when "00011000"=> d<="11100001"  ; when "00011001"=> d<="11101001"  ;
when "00011010"=> d<="11101111"  ;when "00011011"=> d<="11110101"  ;
when "00011100"=> d<="11111001"  ; when "00011101"=> d<="11111100"  ;
when "00011110"=> d<="11111110"  ;when "00011111"=> d<="11111111"  ;

when "00100000"=> d<="11111111"  ; when "00100001"=> d<="11111110"  ;
when "00100010"=> d<="11111100"  ;when "00100011"=> d<="11111001"  ;
when "00100100"=> d<="11110101"  ; when "00100101"=> d<="11101111"  ;
when "00100110"=> d<="11101001"  ;when "00100111"=> d<="11100001"  ;
when "00101000"=> d<="11011001"  ; when "00101001"=> d<="11001111"  ;
when "00101010"=> d<="11000101"  ;when "00101011"=> d<="10111010"  ;
when "00101100"=> d<="10101110"  ; when "00101101"=> d<="10100010"  ;
when "00101110"=> d<="10010110"  ;when "00101111"=> d<="10001001"  ;
when "00110000"=> d<="01111100"  ; when "00110001"=> d<="01110000"  ;
when "00110010"=> d<="01100011"  ;when "00110011"=> d<="01010111"  ;
when "00110100"=> d<="01001011"  ; when "00110101"=> d<="01000000"  ;
when "00110110"=> d<="00110101"  ;when "00110111"=> d<="00101011"  ;
when "00111000"=> d<="00100010"  ; when "00111001"=> d<="00011010"  ;
when "00111010"=> d<="00010011"  ;when "00111011"=> d<="00001101"  ;
when "00111100"=> d<="00001000"  ; when "00111101"=> d<="00000100"  ;
when "00111110"=> d<="00000001"  ;when "00111111"=> d<="00000000"  ;

 when others=>null;
end case;
end process;

end ab;