?? cc1100.lst
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C51 COMPILER V8.02 CC1100 01/09/2008 07:37:30 PAGE 1
C51 COMPILER V8.02, COMPILATION OF MODULE CC1100
OBJECT MODULE PLACED IN CC1100.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE CC1100.c BROWSE DEBUG OBJECTEXTEND
line level source
1 //
2 //CC1100.h
3 //
4 // Copyright (c) NewMSG. All rights reserved. 2007
5 // purpose : Test CC1100
6 // By misswhile
7 #include <reg52.h>
8 #include <intrins.h>
9 #include "CC1100.h"
10
11
12 #define WRITE_BURST 0x40 //連續(xù)寫入
13 #define READ_SINGLE 0x80 //讀
14 #define READ_BURST 0xC0 //連續(xù)讀
15 #define BYTES_IN_RXFIFO 0x7F //接收緩沖區(qū)的有效字節(jié)數(shù)
16 #define CRC_OK 0x80 //CRC校驗(yàn)通過位標(biāo)志
17
18 /****************************************************************************************
19 //全局變量定義
20 /****************************************************************************************/
21 /*
22 //10k E
23 RF_SETTINGS code rfSettings = {
24 0x00,
25 0x06, // FSCTRL1 Frequency synthesizer control.
26 0x00, // FSCTRL0 Frequency synthesizer control.
27 0x10, // FREQ2 Frequency control word, high byte.
28 0xA7, // FREQ1 Frequency control word, middle byte.
29 0x62, // FREQ0 Frequency control word, low byte.
30 0xC8, // MDMCFG4 Modem configuration.
31 0x93, // MDMCFG3 Modem configuration.
32 0x03, // MDMCFG2 Modem configuration.
33 0x22, // MDMCFG1 Modem configuration.
34 0xF8, // MDMCFG0 Modem configuration.
35 0x00, // CHANNR Channel number.
36 0x34, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
37 0x56, // FREND1 Front end RX configuration.
38 0x10, // FREND0 Front end RX configuration.
39 0x18, // MCSM0 Main Radio Control State Machine configuration.
40 0x16, // FOCCFG Frequency Offset Compensation Configuration.
41 0x6C, // BSCFG Bit synchronization Configuration.
42 0x43, // AGCCTRL2 AGC control.
43 0x40, // AGCCTRL1 AGC control.
44 0x91, // AGCCTRL0 AGC control.
45 0xA9, // FSCAL3 Frequency synthesizer calibration.
46 0x2A, // FSCAL2 Frequency synthesizer calibration.
47 0x00, // FSCAL1 Frequency synthesizer calibration.
48 0x11, // FSCAL0 Frequency synthesizer calibration.
49 0x59, // FSTEST Frequency synthesizer calibration.
50 0x81, // TEST2 Various test settings.
51 0x35, // TEST1 Various test settings.
52 0x09, // TEST0 Various test settings.
53 0x0B, // IOCFG2 GDO2 output pin configuration.
54 0x06, // IOCFG0D GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed p
-seudo register explanation.
C51 COMPILER V8.02 CC1100 01/09/2008 07:37:30 PAGE 2
55 0x04, // PKTCTRL1 Packet automation control.
56 0x05, // PKTCTRL0 Packet automation control.
57 0x00, // ADDR Device address.
58 0xFF // PKTLEN Packet length.
59 };
60 */
61 /*
62 // 250k E
63 const RF_SETTINGS rfSettings = {
64 0x00,
65 0x0B, // FSCTRL1 Frequency synthesizer control.
66 0x00, // FSCTRL0 Frequency synthesizer control.
67 0x10, // FREQ2 Frequency control word, high byte.
68 0xA7, // FREQ1 Frequency control word, middle byte.
69 0x62, // FREQ0 Frequency control word, low byte.
70 0x2D, // MDMCFG4 Modem configuration.
71 0x3B, // MDMCFG3 Modem configuration.
72 0x73, // MDMCFG2 Modem configuration.
73 0x22, // MDMCFG1 Modem configuration.
74 0xF8, // MDMCFG0 Modem configuration.
75
76 0x00, // CHANNR Channel number.
77 0x00, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
78 0xB6, // FREND1 Front end RX configuration.
79 0x10, // FREND0 Front end RX configuration.
80 0x18, // MCSM0 Main Radio Control State Machine configuration.
81 0x1D, // FOCCFG Frequency Offset Compensation Configuration.
82 0x1C, // BSCFG Bit synchronization Configuration.
83 0xC7, // AGCCTRL2 AGC control.
84 0x00, // AGCCTRL1 AGC control.
85 0xB2, // AGCCTRL0 AGC control.
86
87 0xEA, // FSCAL3 Frequency synthesizer calibration.
88 0x0A, // FSCAL2 Frequency synthesizer calibration.
89 0x00, // FSCAL1 Frequency synthesizer calibration.
90 0x11, // FSCAL0 Frequency synthesizer calibration.
91 0x59, // FSTEST Frequency synthesizer calibration.
92 0x88, // TEST2 Various test settings.
93 0x31, // TEST1 Various test settings.
94 0x0B, // TEST0 Various test settings.
95 0x0B, // IOCFG2 GDO2 output pin configuration.
96 0x06, // IOCFG0D GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed p
-seudo register explanation.
97
98 0x04, // PKTCTRL1 Packet automation control.
99 0x05, // PKTCTRL0 Packet automation control.
100 0x00, // ADDR Device address.
101 0x0c // PKTLEN Packet length.
102 };
103 */
104
105 /*
106 // 38.4k E
107 const RF_SETTINGS rfSettings = {
108 0x00,
109 0x06, // FSCTRL1 Frequency synthesizer control.
110 0x00, // FSCTRL0 Frequency synthesizer control.
111 0x10, // FREQ2 Frequency control word, high byte.
112 0xA7, // FREQ1 Frequency control word, middle byte.
113 0x62, // FREQ0 Frequency control word, low byte.
114 0xCA, // MDMCFG4 Modem configuration.
115 0x83, // MDMCFG3 Modem configuration.
C51 COMPILER V8.02 CC1100 01/09/2008 07:37:30 PAGE 3
116 0x83, // MDMCFG2 Modem configuration.
117 0x22, // MDMCFG1 Modem configuration.
118 0xF8, // MDMCFG0 Modem configuration.
119
120 0x00, // CHANNR Channel number.
121 0x34, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
122 0x56, // FREND1 Front end RX configuration.
123 0x10, // FREND0 Front end RX configuration.
124 0x18, // MCSM0 Main Radio Control State Machine configuration.
125 0x16, // FOCCFG Frequency Offset Compensation Configuration.
126 0x6C, // BSCFG Bit synchronization Configuration.
127 0x43, // AGCCTRL2 AGC control.
128 0x40, // AGCCTRL1 AGC control.
129 0x91, // AGCCTRL0 AGC control.
130
131 0xA9, // FSCAL3 Frequency synthesizer calibration.
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