#include <asm.h>#include <include/mipsregs.h>#include <include/address.h>/*#define FCR_COM1_BASE  0xbf004080*/#define FCR_COM1_BASE  0xbf004090#define FCR_COM1_DATA  (FCR_COM1_BASE + 0x0)#define FCR_COM1_FCR   (FCR_COM1_BASE + 0x2)#define FCR_COM1_LSR   (FCR_COM1_BASE + 0x5)#define PRINTSTR(x) \        .rdata;98: .asciz x; .text; la a0, 98b; bal puts; nop#define REGSZ		4#define CACHELINE	32#define STKSIZE 0x3000################### UART          ###################define UART_OUTCH(a)	\	li	a0, (a) ; \	bal	tgt_putchar	;\	nop#######################################  ROM Exception Entry	             #######################################	.text	.ent	reset_exceptionreset_exception:	.set noreorder	.set noat	b		start		# Reset Exception Entry	move	k0, zero	.set reorder	.org 0x380		b		excHandler	# General Exception Entry, in ROM						# it located at physaddr 0x1bfc0380	.end	reset_exception	####################################### 		ROM BIOS Entry       #######################################	.comm	stack, STKSIZE		# Stack area 									.set	at	.globl 	start	.ent 	startstart:					# This is the entry point of the BIOS ROM Image.	.globl 	__start__start:	move	k0, zero########################################### 	Force Code to Run in K1 Seg.	 ##	Now the cache of CPU is invalid  ###########################################	.set	noreorder	.set	nomacro	bal		1f	lui		t0, K1BASE>>16		# in fact, here a nop instruction inserted1:	or		ra, t0			# by compiler in case of the delay slots effect.	addiu		ra, 16			# 16 = 4 * sizeof(LX-1 inst size).	j		ra			# now ra = . + 1	nop	.set	macro	.set	reorder	####################################### 	Set up a K1seg stack         #######################################	.set reorder1:	la      sp, stack + STKSIZE - 24	or      sp, sp, K1BASE#######################################   Calculate Re-location code	     #######################################	bal		1f1:	la		t1, 1b			# Little trick to calculate relocation offset.	subu		s8, ra, t1	#if 1##################################   Init COM Port in fcr soc    ##################################	li	a0, FCR_COM1_BASE	li		t1, 0x80	# set DLAB = 1	addu	a2, a0, 3					sb		t1, (a2)	# LCR (Line Control Register)#	li		t1, 0xD9        # Crystal:33.3MHz, Baudrate = 9600bps ->0xD9	li		t1, 0x6C        # Crystal:16.6MHz, Baudrate = 9600bps ->0x6C	addu	a2, a0, 0	sb		t1, (a2)	# DLL (Divide Latch, LSB)		li		t1, 0x00	# Baudrate=9600. MSB should be 0	addu	a2, a0, 1	sb		t1, (a2)	# DLM (Divisor Latch, MSB) 	li		t1, 0x0b	# 8N1	addu	a2, a0, 3	sb		t1, (a2)	# LCR (Line Control Register)		li		t1, 0x47	# RCVR Trigger & FIFO Enable	addu	a2, a0, 2		# reset Tx/Rx Fifo	sb		t1, (a2)	# FCR (Fifo Control Register)#endif	UART_OUTCH('S')	UART_OUTCH('T')	UART_OUTCH('A')	UART_OUTCH('R')	UART_OUTCH('T')	UART_OUTCH('.')	UART_OUTCH('.')#################################   Initailize SDRAM Interface #################################        li  a0,0xbf000000#config	li a1, 0x20000000	    sw  a1,4(a0)#timing	li  a1,0x01040242    sw  a1,0(a0)#config	li a1, 0x209800c6	    sw  a1,4(a0)#	bal doMemTestX	# test SDRAM module####################################### 	ROM => RAM, Text RAM Section #######################################	la		t0, _ftext	add		t0, s8		# t0 = ROM addr of text segs end	la		t1, _ftext	# t1	destination	t1  	or		t1, K1BASE	la		t2,_etext	# t2 is the length of textram+rodat segs.	or		t2, K1BASE	addu	t2, REGSZ - 1	and		t2, -REGSZ		# end address aligned	.set	noreorder1:	lw		t3, 0(t0)		# t3: source context	addu	t0, REGSZ			# t0: source address register	addu	t1, REGSZ			# t1: destination address register	bne		t1, t2, 1b		# t2: end address register    	 sw		t3, -REGSZ(t1)####################################### 	ROM => RAM, Data  Sections   #######################################	.set	reorder2:	la		t0, _etext	addu	t0, s8			# RELOC	or		t0, K1BASE	# t0: data section start address in ROM	la		t1, _etext	or		t1, K1BASE	# t1: data section start address in RAM	la		t2, _edata	or		t2, K1BASE	# t2: data section end address in RAM	beq		t1, t2, zbss	.set	noreorder1:	lw		t3, 0(t0)	addu	t0, REGSZ	addu	t1, REGSZ	bne		t1, t2, 1b    	 sw		t3, -REGSZ(t1)####################################### 	  Clean BSS sections         #######################################	.set	reorderzbss:		# clear bss	la		v0, _fbss		# BSS section pre-compiled start in RAM	la		v1, end			# BSS section pre-compiled end in RAM	or		v0, K1BASE	or		v1, K1BASE	1:	.set	noreorder	sw		$0, 0(v0)	sw		$0, 4(v0)	sw		$0, 8(v0)	addu	v0, 16	bltu	v0, v1, 1b	sw		$0, -4(v0)		# use delay slot to fill 12(v0)####################################### Copy Exception Vectors to RAM      #######################################	.set	reorder	la      a0, excHandler	la      a1, eExcHandler	li      a2, 0x0000180           	bal     copyExcVec	nop#######################################     Disable Interrupt              #######################################	mfc0	t0, CP0_STATUS	and 	t0, 0xfffffffe	# By default it will be disabled.	mtc0	t0, CP0_STATUS	# Set CPU to disable interrupt.	nop	####################################### 	  Init&Flush the Cache of CPU	 #######################################	mfc0	t0, CP0_CONFIG	and		t0, 0xfffffff8	or		t0, 0x2			# disable,!default value is not it!	mtc0	t0, CP0_CONFIG			# Set CPU to disable cache.	nop####################################### Re-set stack pointer for C code    #######################################	la      sp, stack + STKSIZE - 24	# Re-Set stack pointer####################################### 	Jump to normal BIOS startup code #	  #######################################	la		a0, start_bios	la		a0, initmips	jr		a0	nop1:		bal		1b	nop	j		start	.end start################################################### 	copyExcVec Function Entry		 ##						 ##	Params:					 ##		a0 = Src ExcVec Start Addr	 ##		a1 = Src ExcVec End   Addr	 ##		a2 = Dst ExcVec Addr		 ##	Volatile:				 ##		a0, a1				 ###################################################	.globl copyExcVec	.ent copyExcVec	copyExcVec:	or      t0, a0, K1BASE			# Force a0&a1 to K1 Seg	or      t1, a1, K1BASE	or      a2, K1BASE			# Although a2 in K1, but it is in RAM1:  lw      v0, (t0)	sw      v0, (a2)	addu    t0, REGSZ	addu    a2, REGSZ	bltu    t0, t1, 1b	j       ra	.end copyExcVec####################################### 	General Exception Handler Entry  #######################################	.globl 	excHandler	.ent 	excHandler#if __mips >= 3	.align	3#endif	excHandler:	.set noat	PRINTSTR("EXCEPTION!CAUSE=");	mfc0	a0, CP0_CAUSE	la	t1, put32	jalr    t1 	nop	PRINTSTR(" EPC=");	mfc0	a0, CP0_EPC	la	t1, put32	jalr	t1	nop	PRINTSTR(" BADVADDR=");	mfc0	a0, CP0_BADVADDR	la 	t1, put32	jalr	t1	nop	PRINTSTR(" STATUS=");	mfc0	a0, CP0_STATUS	la 	t1, put32	jalr	t1	nop		.set mips3	eret	.set mips0eExcHandler:					# End of General Exception Handler	.set at	.end excHandler#define TXWAIT		(0x13)#define __TXWAIT	(0x12)/* destroy: t0,t1,ra */LEAF(tgt_putchar)	.set noreorder   	li	t0, TXWAIT			# timeout1:	lbu	t1, (FCR_COM1_LSR)		# get LSR	and	t1, 0x20			# tx ready?	bnez	t1, 1f				# can write	nop2:	li	t1, __TXWAIT			# Wait a while3:	subu	t1, 1	bnez	t1, 3b	nop	subu	t0, 1				# continue until timeout 	bnez	t0, 1b	nop1:	sb	a0, (FCR_COM1_DATA)		# write data	j	ra	nopEND(tgt_putchar)####################################### Print 32bit Integer in reg a0      #######################################LEAF(put32)	.set noreorder	move	t9, ra	move	t6, a0	li	t7, 322:	subu	t7, 4	srl a0, t7	and a0, 0x0F	blt	a0, 0x0A, 3f	nop	subu	a0, 0x0a	addu	a0, 'A'	j	4f	nop3:	addu	a0, '0'4:	bal	tgt_putchar	nop	move	a0, t6	bnez	t7, 2b	nop		move	ra, t9	j	ra	nop	.set reorderEND(put32)/* * Simple character printing routine used before full initialization *//* destroy: a0,a1 t0,t1(tgt_putchar), t9 */LEAF(puts)	.set noreorder        move    t9, ra        move    a1, a0        lbu     a0, 0(a1)1:        beqz    a0, 2f        nop        bal     tgt_putchar        addiu   a1, 1        b       1b        lbu     a0, 0(a1)2:        j       t9        nop	.set reorderEND(puts)####################################### 	Test SDRAM Module            #######################################LEAF(doMemTestX)	.set macro	.set noreorder#if 0#define MEM_BOT		(0xA0000000)		/* 64MB */#define MEM_TOP		(0xA4000000)		/* 64MB */#define	MEM_STEP	      (0x04)#else	#define MEM_BOT		(0xA0000000)		/* */#define MEM_TOP		(0xA8000000)		/* 128MB */#define	MEM_STEP	   (0x01000)#endif	move	t9, ra/* Store data into SDRAM */	PRINTSTR("\r\nSDRAM Testing...");	li	a1, 0x0	li	a2, 0x0	li	a3, 0x0	li	s0, 0x1	li	s1, 0x2	li	s2, 0x3	li	s3, 0x4	nop		li	t2, MEM_BOT	li	t3, MEM_TOP1:	sw	s0, (t2)	sh	s1, 4(t2)	sb	s2, 6(t2)	move 	a0,  t2			nop	bal	put32	nop	PRINTSTR("\r\n")	lw	s3, (t2)	bne	s3, s0, 3f	nop	lhu	s4, 4(t2)	and     t4, s1, 0xffff	bne	s4, t4, 3f	nop	lbu	s5, 6(t2)	and     t4, s2, 0xff	bne	s5, t4, 3f	nop	2:	addiu	t2, MEM_STEP	addiu	s0, 0x1	addiu	s1, 0x1	addiu	s2, 0x1	bne	t2, t3, 1b	nop	PRINTSTR("\r\nTest end.\r\n")		move	ra, t9	j	ra	nop######################### some error occured ! #########################3:		PRINTSTR("\r\nMISMATCH at locate:")	move 	a0,  t2			nop	bal	put32	nop	PRINTSTR("\r\nExpect:")	move	a0, s0	bal	put32		nop	UART_OUTCH(' ')	move	a0, s1	bal	put32		nop	UART_OUTCH(' ')	move	a0, s2	bal	put32		nop	PRINTSTR(" Got:")	move	a0, s3 	bal	put32		nop	UART_OUTCH(' ')	move	a0, s4	bal	put32		nop	UART_OUTCH(' ')	move	a0, s5	bal	put32		nop	PRINTSTR("\r\n")	b	2b	nop	.set reorderEND(doMemTestX)