/*	$Id: pci_machdep.c,v 1.2 2003/12/10 09:23:35 wlin Exp $ *//* * Copyright (c) 2001 Opsycon AB  (www.opsycon.se) *  * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright *    notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright *    notice, this list of conditions and the following disclaimer in the *    documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software *    must display the following acknowledgement: *	This product includes software developed by Opsycon AB, Sweden. * 4. The name of the author may not be used to endorse or promote products *    derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */#include <sys/param.h>#include <sys/device.h>#include <sys/systm.h>#include <sys/malloc.h>#include <dev/pci/pcivar.h>#include <dev/pci/pcireg.h>#include <dev/pci/nppbreg.h>#include <machine/bus.h>#include <pmon.h>extern void *pmalloc __P((size_t ));extern int _pciverbose;extern char hwethadr[6];struct pci_device *_pci_bus[16];int _max_pci_bus = 0;/********************************************************************//*initial PCI                                                       *//********************************************************************/int_pci_hwinit (initialise, iot, memt)	int initialise;	bus_space_tag_t iot;	bus_space_tag_t memt;{  return 0;}/* * Called to reinitialise the bridge after we've scanned each PCI device * and know what is possible. We also set up the interrupt controller * routing and level control registers. */void_pci_hwreinit (void){}void_pci_flush (void){}/* *  Map the CPU virtual address of an area of local memory to a PCI *  address that can be used by a PCI bus master to access it. */vm_offset_t_pci_dmamap(va, len)	vm_offset_t va;	unsigned int len;{  return 0;}#if 0/* *  Map the PCI address of an area of local memory to a CPU physical *  address. */vm_offset_t_pci_cpumap(pcia, len)	vm_offset_t pcia;	unsigned int len;{	return PA_TO_VA(pcia - pci_local_mem_pci_base);}#endif/* *  Make pci tag from bus, device and function data. */pcitag_t_pci_make_tag(bus, device, function)	int bus;	int device;	int function;{	pcitag_t tag;	tag = (bus << 16) | (device << 11) | (function << 8);	return(tag);}/* *  Break up a pci tag to bus, device function components. */void_pci_break_tag(tag, busp, devicep, functionp)	pcitag_t tag;	int *busp;	int *devicep;	int *functionp;{	if (busp) {		*busp = (tag >> 16) & 255;	}	if (devicep) {		*devicep = (tag >> 11) & 31;	}	if (functionp) {		*functionp = (tag >> 8) & 7;	}}int_pci_canscan (pcitag_t tag){	int bus, device, function;	_pci_break_tag (tag, &bus, &device, &function); 	if((bus == 0 || bus == 1) && device == 0) {		return(0);		/* Ignore the Discovery itself */	}	return (1);}pcireg_t_pci_conf_read(pcitag_t tag,int reg){	return _pci_conf_readn(tag,reg,4);}pcireg_t_pci_conf_readn(pcitag_t tag, int reg, int width){    return 0;}void_pci_conf_write(pcitag_t tag, int reg, pcireg_t data){	return _pci_conf_writen(tag,reg,data,4);}void_pci_conf_writen(pcitag_t tag, int reg, pcireg_t data,int width){}voidpci_sync_cache(p, adr, size, rw)	void *p;	vm_offset_t adr;	size_t size;	int rw;{	CPU_IOFlushDCache(adr, size, rw);}