/*	$Id: starto.S,v 1.7 2004/05/27 04:14:49 wlin Exp $ *//* * Copyright (c) 2001 Opsycon AB  (www.opsycon.se) *  * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright *    notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright *    notice, this list of conditions and the following disclaimer in the *    documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software *    must display the following acknowledgement: *	This product includes software developed by Opsycon AB, Sweden. * 4. The name of the author may not be used to endorse or promote products *    derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */#ifndef _KERNEL#define _KERNEL#endif#include <asm.h>#include <regnum.h>#include <cpu.h>#include <pte.h>#include "target/it8172.h"#include "pmon/dev/ns16550.h"#define DEBUG_LOCORE#ifdef DEBUG_LOCORE#define	TTYDBG(x) \	.rdata;98: .asciz x; .text; la a0, 98b; bal stringserial; nop#else#define TTYDBG(x)#endif#define	PRINTSTR(x) \	.rdata;98: .asciz x; .text; la a0, 98b; bal stringserial; nop/* *   Register usage: * *	s0	link versus load offset, used to relocate absolute adresses. *	s1	free *	s2	base address to ITE chip. *	s3	L1 I cache size. *	s4	L1 I cache line size. *	s5	L1 D cache size. *	s6	L1 D cache line size. *	s7	L2 Cache size. *	s8	L3 Cache size. */	.set	noreorder	.globl	_start	.globl	start	.globl	__main_start:start:	.globl	stackstack = start - 0x4000		/* Place PMON stack below PMON start in RAM *//* NOTE!! Not more that 16 instructions here!!! Right now it's FULL! */	la	sp, stack	la	gp, _gp	bal	uncached		/* Switch to uncached address space */	nop	bal	locate			/* Get current execute address */	nopuncached:	or	ra, UNCACHED_MEMORY_ADDR	j	ra	nop/* *  Reboot vector usable from outside pmon. */	.align	8ext_map_and_reboot:	bal	CPU_TLBClear	nop	li	a0, 0xc0000000	li	a1, 0x40000000	bal	CPU_TLBInit	nop	la	v0, tgt_reboot	la	v1, start	subu	v0, v1	lui	v1, 0xffc0	addu	v0, v1	jr	v0	nop/* *  Exception vectors here for rom, before we are up and running. Catch *  whatever comes up before we have a fully fledged exception handler. */	.align	9			/* bfc00200 */	la	a0, v200_msg	bal	stringserial	nop	b	exc_common	.align	7			/* bfc00280 */	la	a0, v280_msg	bal	stringserial	nop	b	exc_common/* Cache error */	.align	8			/* bfc00300 */	PRINTSTR("\r\nPANIC! Unexpected Cache Error exception! ")	mfc0	a0, COP_0_CACHE_ERR	bal	hexserial	nop	b	exc_common/* General exception */	.align	7			/* bfc00380 */	la	a0, v380_msg	bal	stringserial	nop	b	exc_common	.align	8			/* bfc00400 */	la	a0, v400_msg	bal	stringserial	nopexc_common:	PRINTSTR("\r\nERRORPC=")	mfc0	a0, COP_0_ERROR_PC	bal	hexserial	nop	PRINTSTR("\r\nEPC=")	mfc0	a0, COP_0_EXC_PC	bal	hexserial	nop	PRINTSTR("\r\n(EPC)=")	mfc0	a0, COP_0_EXC_PC	lw	a0, (a0)	bal	hexserial	nop	PRINTSTR("\r\nSTATUS=")	mfc0	a0, COP_0_STATUS_REG	bal	hexserial	nop	PRINTSTR("\r\nCAUSE=")	mfc0	a0, COP_0_CAUSE_REG	bal	hexserial	nop	PRINTSTR("\r\nBADVADDR=")#if __mips >= 3	dmfc0	a0, $8        dsrl  a0,a0,32	bal	hexserial        nop#endif	mfc0	a0, $8	bal	hexserial	nop	PRINTSTR("\r\nDERR0=")	cfc0	a0, COP_0_DERR_0	bal	hexserial	nop	PRINTSTR("\r\nDERR1=")	cfc0	a0, COP_0_DERR_1	bal	hexserial	nop		1:	 b  1b        nop	 //	b	ext_map_and_reboot	nop/* * gpio function define          */#define GPIO_LOOP       10000#define MK_LAT(v)\        li              t0, (v);        \9:      subu    t0, 1;          \        bne             t0, 0, 9b;      \        nop;#if 1#define FLASH_GPIO(a)   \        li      a0, (a)         ;\        bal     __flash_gpio    ;\        nop#else#define FLASH_GPIO(a)   \        li      t1, 0xb4013802;\        li      t0, 0x550       ;\        sh      t0, (t1)        ;\        subu    t1, t1, 2;\        li      t0, (a)         ;\        sll     t0, 2           ;\        sb      t0, (t1);       \        MK_LAT(GPIO_LOOP);#endif/*  * LED       */    #define FLASH_LED(a)    \        li      a0, (a)         ;\        bal     __led_display   ;\        nop/* *  We get here from executing a bal to get the PC value of the current execute *  location into ra. Check to see if we run from ROM or if this is ramloaded. */	.align 8    /*bfc00500*/	.word read	.word write	.word open	.word close	.word nullfunction	.word printf	.word vsprintf	.word nullfunction	.word nullfunction	.word getenv	.word nullfunction	.word nullfunction	.word nullfunction	.word nullfunction	locate:	bal init_regs	nop	la	s0, start		/* RA set from BAL above! */	subu	s0, ra, s0		/* s0 is now load vs. link offset */	and	s0, 0xffff0000		/* Mask off lower bits *//* * Initialize Configuration for board */        mfc0    t1, COP_0_STATUS_REG                   mtc0    zero, COP_0_CAUSE_REG                  and             t1, SR_SOFT_RESET       #        or              t1, SR_BOOT_EXC_VEC      # Should be omited because it has been done before        mtc0    t1, COP_0_STATUS_REG           # Set STATUS Reg	li	t1, 0xa000038c	mtc0	t1, COP_0_ERROR_PC        nop/* *  Init serial I/O for diagnostic output. */        bal     initserial        nop        PRINTSTR("\r\nPMON2000 MIPS Initializing. Standby...\r\n")        PRINTSTR("ERRORPC=")        mfc0    a0, COP_0_ERROR_PC        bal     hexserial        nop        FLASH_GPIO(0x04)                # GPD 2..4 => 0001        PRINTSTR(" CONFIG=")        mfc0    a0, COP_0_CONFIG        bal     hexserial        nop        PRINTSTR("\r\n")        la      s0, start               /* RA set from BAL above! */        subu    s0, ra, s0              /* s0 is now load vs. link offset */        and     s0, 0xffff0000          /* Mask off lower bits */        //TTYDBG("Setting up SDRAM controller\r\n");/* *  Reset and initialize caches to a known state. */#define IndexStoreTagI	0x08#define IndexStoreTagD	0x09#define IndexStoreTagS	0x0b#define IndexStoreTagT	0x0a#define FillI		0x14#if 0/* *  Clean out and initialize the TLB */	bal	CPU_TLBClear	nop	li	a0, 0xc0000000	li	a1, 0x40000000	bal	CPU_TLBInit	nop#endif /* Initialize Cache */	TTYDBG("Cache initializing..\r\n")	bal godson2_cache_init	nop	TTYDBG("Done\r\n")/* Memory test */#	bal mem_test#	nop/* *  At this point all memory controller setup should have been done *  and we should be able to function 'normally' and C code can be *  used freely from this point. *//* If use compression all the datas have been already loaded into memory */#if 0	la	a0, start	li	a1, 0xbfc00000	la	a2, _edata	subu	t1, a2, a0	srl     t1, t1, 2	/* copy text section */	li	t0, 01:	lw	v0, 0(a1)	nop	sw	v0, 0(a0)	move 	t1, a0	lw	a0, 0(t1)	bal	hexserial	nop	move	a0, t1	addu	a0, 4	bne a2, a0, 1b	addu	a1, 4#endif		/* Clear BSS */	la	a0, _edata	la	a2, _end	or	a0, KSEG1	or	a2, KSEG1	2:	sw	zero, 0(a0)	bgt 	a2, a0, 2b	addu	a0, 4	TTYDBG("Copy PMON to execute location done.\r\n")	li	a0,0x04000000 /* 64Mb */	nop	la	v0, initmips	nop	jalr	v0	nopstuck:#ifdef DEBUG_LOCORE	TTYDBG("Dumping IT8172 setup.\r\n")	TTYDBG("offset----data------------------------.\r\n")	li	s3, 01:	move	a0, s3	bal	hexserial	nop	TTYDBG(": ")2:	add	a0, s3, s2	lw	a0, 0(a0)	bal	hexserial	addiu	s3, 4	TTYDBG(" ")	li	a0, 0xfff	and	a0, s3	beqz	a0, 3f	li	a0, 0x01f	and	a0, s3	bnez	a0, 2b	TTYDBG("\r\n")	b	1b	nop3:	b	3b	nop#else	b	stuck	nop#endif